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-rw-r--r--src/dev/ide_ctrl.cc232
-rw-r--r--src/dev/ide_ctrl.hh8
-rw-r--r--src/dev/ide_disk.cc8
-rw-r--r--src/dev/io_device.cc183
-rw-r--r--src/dev/io_device.hh90
-rw-r--r--src/dev/ns_gige.cc55
-rw-r--r--src/dev/ns_gige.hh8
-rw-r--r--src/dev/pciconfigall.cc131
-rw-r--r--src/dev/pciconfigall.hh66
-rw-r--r--src/dev/pcidev.cc357
-rw-r--r--src/dev/pcidev.hh117
-rw-r--r--src/dev/pcireg.h1
-rw-r--r--src/dev/platform.cc16
-rw-r--r--src/dev/platform.hh16
-rw-r--r--src/dev/sinic.cc20
-rw-r--r--src/dev/sinic.hh1
-rw-r--r--src/dev/tsunami.cc7
-rw-r--r--src/dev/tsunami.hh6
-rw-r--r--src/dev/tsunami_pchip.cc11
-rw-r--r--src/dev/tsunami_pchip.hh5
20 files changed, 730 insertions, 608 deletions
diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc
index 63435e87c..5ffc02d34 100644
--- a/src/dev/ide_ctrl.cc
+++ b/src/dev/ide_ctrl.cc
@@ -227,177 +227,143 @@ IdeController::setDmaComplete(IdeDisk *disk)
// Read and write handling
////
-void
-IdeController::readConfig(int offset, uint8_t *data)
+Tick
+IdeController::readConfig(Packet *pkt)
{
- if (offset < PCI_DEVICE_SPECIFIC) {
- PciDev::readConfig(offset, data);
- } else if (offset >= IDE_CTRL_CONF_START &&
- (offset + 1) <= IDE_CTRL_CONF_END) {
+ int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
+ if (offset < PCI_DEVICE_SPECIFIC)
+ return PciDev::readConfig(pkt);
+ assert(offset >= IDE_CTRL_CONF_START && (offset + 1) <= IDE_CTRL_CONF_END);
+ pkt->allocate();
+
+ switch (pkt->getSize()) {
+ case sizeof(uint8_t):
switch (offset) {
case IDE_CTRL_CONF_DEV_TIMING:
- *data = config_regs.sidetim;
+ pkt->set<uint8_t>(config_regs.sidetim);
break;
case IDE_CTRL_CONF_UDMA_CNTRL:
- *data = config_regs.udmactl;
+ pkt->set<uint8_t>(config_regs.udmactl);
break;
case IDE_CTRL_CONF_PRIM_TIMING+1:
- *data = htole(config_regs.idetim0) >> 8;
+ pkt->set<uint8_t>(htole(config_regs.idetim0) >> 8);
break;
case IDE_CTRL_CONF_SEC_TIMING+1:
- *data = htole(config_regs.idetim1) >> 8;
+ pkt->set<uint8_t>(htole(config_regs.idetim1) >> 8);
break;
case IDE_CTRL_CONF_IDE_CONFIG:
- *data = htole(config_regs.ideconfig) & 0xFF;
+ pkt->set<uint8_t>(htole(config_regs.ideconfig) & 0xFF);
break;
case IDE_CTRL_CONF_IDE_CONFIG+1:
- *data = htole(config_regs.ideconfig) >> 8;
+ pkt->set<uint8_t>(htole(config_regs.ideconfig) >> 8);
break;
default:
panic("Invalid PCI configuration read for size 1 at offset: %#x!\n",
offset);
}
-
- } else {
- panic("Read of unimplemented PCI config. register: %x\n", offset);
- }
- DPRINTF(IdeCtrl, "PCI read offset: %#x size: 1 data: %#x\n",
- offset, (uint32_t)*data);
-}
-
-void
-IdeController::readConfig(int offset, uint16_t *data)
-{
- if (offset < PCI_DEVICE_SPECIFIC) {
- PciDev::readConfig(offset, data);
- } else if (offset >= IDE_CTRL_CONF_START &&
- (offset + 2) <= IDE_CTRL_CONF_END) {
-
+ DPRINTF(IdeCtrl, "PCI read offset: %#x size: 1 data: %#x\n", offset,
+ (uint32_t)pkt->get<uint8_t>());
+ break;
+ case sizeof(uint16_t):
switch (offset) {
case IDE_CTRL_CONF_PRIM_TIMING:
- *data = config_regs.idetim0;
+ pkt->set<uint16_t>(config_regs.idetim0);
break;
case IDE_CTRL_CONF_SEC_TIMING:
- *data = config_regs.idetim1;
+ pkt->set<uint16_t>(config_regs.idetim1);
break;
case IDE_CTRL_CONF_UDMA_TIMING:
- *data = config_regs.udmatim;
+ pkt->set<uint16_t>(config_regs.udmatim);
break;
case IDE_CTRL_CONF_IDE_CONFIG:
- *data = config_regs.ideconfig;
+ pkt->set<uint16_t>(config_regs.ideconfig);
break;
default:
panic("Invalid PCI configuration read for size 2 offset: %#x!\n",
offset);
}
-
- } else {
- panic("Read of unimplemented PCI config. register: %x\n", offset);
+ DPRINTF(IdeCtrl, "PCI read offset: %#x size: 2 data: %#x\n", offset,
+ (uint32_t)pkt->get<uint16_t>());
+ break;
+ case sizeof(uint32_t):
+ panic("No 32bit reads implemented for this device.");
+ DPRINTF(IdeCtrl, "PCI read offset: %#x size: 4 data: %#x\n", offset,
+ (uint32_t)pkt->get<uint32_t>());
+ break;
+ default:
+ panic("invalid access size(?) for PCI configspace!\n");
}
- DPRINTF(IdeCtrl, "PCI read offset: %#x size: 2 data: %#x\n", offset, *data);
-}
+ pkt->result = Packet::Success;
+ return configDelay;
-void
-IdeController::readConfig(int offset, uint32_t *data)
-{
- if (offset < PCI_DEVICE_SPECIFIC) {
- PciDev::readConfig(offset, data);
- } else {
- panic("Read of unimplemented PCI config. register: %x\n", offset);
- }
- DPRINTF(IdeCtrl, "PCI read offset: %#x size: 4 data: %#x\n", offset, *data);
}
-void
-IdeController::writeConfig(int offset, const uint8_t data)
-{
- if (offset < PCI_DEVICE_SPECIFIC) {
- PciDev::writeConfig(offset, data);
- } else if (offset >= IDE_CTRL_CONF_START &&
- (offset + 1) <= IDE_CTRL_CONF_END) {
- switch (offset) {
- case IDE_CTRL_CONF_DEV_TIMING:
- config_regs.sidetim = data;
- break;
- case IDE_CTRL_CONF_UDMA_CNTRL:
- config_regs.udmactl = data;
- break;
- case IDE_CTRL_CONF_IDE_CONFIG:
- config_regs.ideconfig = (config_regs.ideconfig & 0xFF00) | (data);
- break;
- case IDE_CTRL_CONF_IDE_CONFIG+1:
- config_regs.ideconfig = (config_regs.ideconfig & 0x00FF) | data << 8;
- break;
- default:
- panic("Invalid PCI configuration write for size 1 offset: %#x!\n",
- offset);
- }
- } else {
- panic("Read of unimplemented PCI config. register: %x\n", offset);
- }
- DPRINTF(IdeCtrl, "PCI write offset: %#x size: 1 data: %#x\n",
- offset, (uint32_t)data);
-}
-
-void
-IdeController::writeConfig(int offset, const uint16_t data)
+Tick
+IdeController::writeConfig(Packet *pkt)
{
+ int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC) {
- PciDev::writeConfig(offset, data);
- } else if (offset >= IDE_CTRL_CONF_START &&
- (offset + 2) <= IDE_CTRL_CONF_END) {
+ PciDev::writeConfig(pkt);
+ } else {
+ assert(offset >= IDE_CTRL_CONF_START && (offset + 1) <= IDE_CTRL_CONF_END);
- switch (offset) {
- case IDE_CTRL_CONF_PRIM_TIMING:
- config_regs.idetim0 = data;
- break;
- case IDE_CTRL_CONF_SEC_TIMING:
- config_regs.idetim1 = data;
+ switch (pkt->getSize()) {
+ case sizeof(uint8_t):
+ switch (offset) {
+ case IDE_CTRL_CONF_DEV_TIMING:
+ config_regs.sidetim = pkt->get<uint8_t>();
+ break;
+ case IDE_CTRL_CONF_UDMA_CNTRL:
+ config_regs.udmactl = pkt->get<uint8_t>();
+ break;
+ case IDE_CTRL_CONF_IDE_CONFIG:
+ config_regs.ideconfig = (config_regs.ideconfig & 0xFF00) |
+ (pkt->get<uint8_t>());
+ break;
+ case IDE_CTRL_CONF_IDE_CONFIG+1:
+ config_regs.ideconfig = (config_regs.ideconfig & 0x00FF) |
+ pkt->get<uint8_t>() << 8;
+ break;
+ default:
+ panic("Invalid PCI configuration write for size 1 offset: %#x!\n",
+ offset);
+ }
+ DPRINTF(IdeCtrl, "PCI write offset: %#x size: 1 data: %#x\n",
+ offset, (uint32_t)pkt->get<uint8_t>());
break;
- case IDE_CTRL_CONF_UDMA_TIMING:
- config_regs.udmatim = data;
+ case sizeof(uint16_t):
+ switch (offset) {
+ case IDE_CTRL_CONF_PRIM_TIMING:
+ config_regs.idetim0 = pkt->get<uint16_t>();
+ break;
+ case IDE_CTRL_CONF_SEC_TIMING:
+ config_regs.idetim1 = pkt->get<uint16_t>();
+ break;
+ case IDE_CTRL_CONF_UDMA_TIMING:
+ config_regs.udmatim = pkt->get<uint16_t>();
+ break;
+ case IDE_CTRL_CONF_IDE_CONFIG:
+ config_regs.ideconfig = pkt->get<uint16_t>();
+ break;
+ default:
+ panic("Invalid PCI configuration write for size 2 offset: %#x!\n",
+ offset);
+ }
+ DPRINTF(IdeCtrl, "PCI write offset: %#x size: 2 data: %#x\n",
+ offset, (uint32_t)pkt->get<uint16_t>());
break;
- case IDE_CTRL_CONF_IDE_CONFIG:
- config_regs.ideconfig = data;
+ case sizeof(uint32_t):
+ panic("Write of unimplemented PCI config. register: %x\n", offset);
break;
default:
- panic("Invalid PCI configuration write for size 2 offset: %#x!\n",
- offset);
+ panic("invalid access size(?) for PCI configspace!\n");
}
-
- } else {
- panic("Write of unimplemented PCI config. register: %x\n", offset);
}
- DPRINTF(IdeCtrl, "PCI write offset: %#x size: 2 data: %#x\n", offset, data);
-
- /* Trap command register writes and enable IO/BM as appropriate. */
- if (offset == PCI_COMMAND) {
- if (letoh(config.command) & PCI_CMD_IOSE)
- io_enabled = true;
- else
- io_enabled = false;
-
- if (letoh(config.command) & PCI_CMD_BME)
- bm_enabled = true;
- else
- bm_enabled = false;
- }
-
-}
-
-void
-IdeController::writeConfig(int offset, const uint32_t data)
-{
- if (offset < PCI_DEVICE_SPECIFIC) {
- PciDev::writeConfig(offset, data);
- } else {
- panic("Read of unimplemented PCI config. register: %x\n", offset);
- }
-
- DPRINTF(IdeCtrl, "PCI write offset: %#x size: 4 data: %#x\n", offset, data);
+ /* Trap command register writes and enable IO/BM as appropriate as well as
+ * BARs. */
switch(offset) {
case PCI0_BASE_ADDR0:
if (BARAddrs[0] != 0)
@@ -423,9 +389,24 @@ IdeController::writeConfig(int offset, const uint32_t data)
if (BARAddrs[4] != 0)
bmi_addr = BARAddrs[4];
break;
+
+ case PCI_COMMAND:
+ if (letoh(config.command) & PCI_CMD_IOSE)
+ io_enabled = true;
+ else
+ io_enabled = false;
+
+ if (letoh(config.command) & PCI_CMD_BME)
+ bm_enabled = true;
+ else
+ bm_enabled = false;
+ break;
}
+ pkt->result = Packet::Success;
+ return configDelay;
}
+
Tick
IdeController::read(Packet *pkt)
{
@@ -770,7 +751,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
SimObjectParam<System *> system;
SimObjectParam<Platform *> platform;
- SimObjectParam<PciConfigAll *> configspace;
SimObjectParam<PciConfigData *> configdata;
Param<uint32_t> pci_bus;
Param<uint32_t> pci_dev;
@@ -784,7 +764,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
INIT_PARAM(system, "System pointer"),
INIT_PARAM(platform, "Platform pointer"),
- INIT_PARAM(configspace, "PCI Configspace"),
INIT_PARAM(configdata, "PCI Config data"),
INIT_PARAM(pci_bus, "PCI bus ID"),
INIT_PARAM(pci_dev, "PCI device number"),
@@ -800,7 +779,6 @@ CREATE_SIM_OBJECT(IdeController)
params->name = getInstanceName();
params->platform = platform;
params->system = system;
- params->configSpace = configspace;
params->configData = configdata;
params->busNum = pci_bus;
params->deviceNum = pci_dev;
diff --git a/src/dev/ide_ctrl.hh b/src/dev/ide_ctrl.hh
index 1d30c8b31..5842d322e 100644
--- a/src/dev/ide_ctrl.hh
+++ b/src/dev/ide_ctrl.hh
@@ -204,12 +204,8 @@ class IdeController : public PciDev
IdeController(Params *p);
~IdeController();
- virtual void writeConfig(int offset, const uint8_t data);
- virtual void writeConfig(int offset, const uint16_t data);
- virtual void writeConfig(int offset, const uint32_t data);
- virtual void readConfig(int offset, uint8_t *data);
- virtual void readConfig(int offset, uint16_t *data);
- virtual void readConfig(int offset, uint32_t *data);
+ virtual Tick writeConfig(Packet *pkt);
+ virtual Tick readConfig(Packet *pkt);
void setDmaComplete(IdeDisk *disk);
diff --git a/src/dev/ide_disk.cc b/src/dev/ide_disk.cc
index dc78021f8..12564ddd0 100644
--- a/src/dev/ide_disk.cc
+++ b/src/dev/ide_disk.cc
@@ -318,7 +318,7 @@ IdeDisk::doDmaTransfer()
panic("Inconsistent DMA transfer state: dmaState = %d devState = %d\n",
dmaState, devState);
- if (ctrl->dmaPending()) {
+ if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
dmaTransferEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
return;
} else
@@ -398,8 +398,7 @@ IdeDisk::doDmaRead()
curPrd.getByteCount(), TheISA::PageBytes);
}
- if (ctrl->dmaPending()) {
- panic("shouldn't be reentant??");
+ if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
dmaReadWaitEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
return;
} else if (!dmaReadCG->done()) {
@@ -474,8 +473,7 @@ IdeDisk::doDmaWrite()
dmaWriteCG = new ChunkGenerator(curPrd.getBaseAddr(),
curPrd.getByteCount(), TheISA::PageBytes);
}
- if (ctrl->dmaPending()) {
- panic("shouldn't be reentant??");
+ if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
dmaWriteWaitEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
return;
} else if (!dmaWriteCG->done()) {
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index 485216874..660efabfd 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -32,10 +32,12 @@
#include "base/trace.hh"
#include "dev/io_device.hh"
#include "sim/builder.hh"
+#include "sim/system.hh"
-PioPort::PioPort(PioDevice *dev, Platform *p)
- : Port(dev->name() + "-pioport"), device(dev), platform(p)
+PioPort::PioPort(PioDevice *dev, System *s, std::string pname)
+ : Port(dev->name() + pname), device(dev), sys(s),
+ outTiming(0), drainEvent(NULL)
{ }
@@ -62,34 +64,68 @@ PioPort::getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
void
PioPort::recvRetry()
{
- Packet* pkt = transmitList.front();
- if (Port::sendTiming(pkt)) {
- transmitList.pop_front();
+ bool result = true;
+ while (result && transmitList.size()) {
+ result = Port::sendTiming(transmitList.front());
+ if (result)
+ transmitList.pop_front();
}
+ if (transmitList.size() == 0 && drainEvent) {
+ drainEvent->process();
+ drainEvent = NULL;
+ }
}
-
void
PioPort::SendEvent::process()
{
+ port->outTiming--;
+ assert(port->outTiming >= 0);
if (port->Port::sendTiming(packet))
- return;
+ if (port->transmitList.size() == 0 && port->drainEvent) {
+ port->drainEvent->process();
+ port->drainEvent = NULL;
+ }
+ return;
port->transmitList.push_back(packet);
}
+void
+PioPort::resendNacked(Packet *pkt) {
+ pkt->reinitNacked();
+ if (transmitList.size()) {
+ transmitList.push_front(pkt);
+ } else {
+ if (!Port::sendTiming(pkt))
+ transmitList.push_front(pkt);
+ }
+};
bool
PioPort::recvTiming(Packet *pkt)
{
- Tick latency = device->recvAtomic(pkt);
- // turn packet around to go back to requester
- pkt->makeTimingResponse();
- sendTiming(pkt, latency);
+ if (pkt->result == Packet::Nacked) {
+ resendNacked(pkt);
+ } else {
+ Tick latency = device->recvAtomic(pkt);
+ // turn packet around to go back to requester
+ pkt->makeTimingResponse();
+ sendTiming(pkt, latency);
+ }
return true;
}
+unsigned int
+PioPort::drain(Event *de)
+{
+ if (outTiming == 0 && transmitList.size() == 0)
+ return 0;
+ drainEvent = de;
+ return 1;
+}
+
PioDevice::~PioDevice()
{
if (pioPort)
@@ -104,6 +140,19 @@ PioDevice::init()
pioPort->sendStatusChange(Port::RangeChange);
}
+
+unsigned int
+PioDevice::drain(Event *de)
+{
+ unsigned int count;
+ count = pioPort->drain(de);
+ if (count)
+ changeState(Draining);
+ else
+ changeState(Drained);
+ return count;
+}
+
void
BasicPioDevice::addressRanges(AddrRangeList &range_list)
{
@@ -113,8 +162,9 @@ BasicPioDevice::addressRanges(AddrRangeList &range_list)
}
-DmaPort::DmaPort(DmaDevice *dev, Platform *p)
- : Port(dev->name() + "-dmaport"), device(dev), platform(p), pendingCount(0)
+DmaPort::DmaPort(DmaDevice *dev, System *s)
+ : Port(dev->name() + "-dmaport"), device(dev), sys(s), pendingCount(0),
+ actionInProgress(0), drainEvent(NULL)
{ }
bool
@@ -144,6 +194,11 @@ DmaPort::recvTiming(Packet *pkt)
}
delete pkt->req;
delete pkt;
+
+ if (pendingCount == 0 && drainEvent) {
+ drainEvent->process();
+ drainEvent = NULL;
+ }
} else {
panic("Got packet without sender state... huh?\n");
}
@@ -155,6 +210,29 @@ DmaDevice::DmaDevice(Params *p)
: PioDevice(p), dmaPort(NULL)
{ }
+
+unsigned int
+DmaDevice::drain(Event *de)
+{
+ unsigned int count;
+ count = pioPort->drain(de) + dmaPort->drain(de);
+ if (count)
+ changeState(Draining);
+ else
+ changeState(Drained);
+ return count;
+}
+
+unsigned int
+DmaPort::drain(Event *de)
+{
+ if (pendingCount == 0)
+ return 0;
+ drainEvent = de;
+ return 1;
+}
+
+
void
DmaPort::recvRetry()
{
@@ -180,6 +258,8 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
{
assert(event);
+ assert(device->getState() == SimObject::Running);
+
DmaReqState *reqState = new DmaReqState(event, this, size);
for (ChunkGenerator gen(addr, size, peerBlockSize());
@@ -197,51 +277,54 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
pendingCount++;
sendDma(pkt);
}
+
}
void
DmaPort::sendDma(Packet *pkt, bool front)
{
- // some kind of selction between access methods
- // more work is going to have to be done to make
- // switching actually work
- /* MemState state = device->platform->system->memState;
-
- if (state == Timing) { */
- DPRINTF(DMA, "Attempting to send Packet %#x with addr: %#x\n",
- pkt, pkt->getAddr());
- if (transmitList.size() || !sendTiming(pkt)) {
- if (front)
- transmitList.push_front(pkt);
- else
- transmitList.push_back(pkt);
- DPRINTF(DMA, "-- Failed: queued\n");
- } else {
- DPRINTF(DMA, "-- Done\n");
- }
- /* } else if (state == Atomic) {
- sendAtomic(pkt);
- if (pkt->senderState) {
- DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState);
- assert(state);
- state->completionEvent->schedule(curTick + (pkt->time -
- pkt->req->getTime()) +1);
- delete state;
- }
- pendingCount--;
- assert(pendingCount >= 0);
- delete pkt->req;
- delete pkt;
-
- } else if (state == Functional) {
- sendFunctional(pkt);
- // Is this correct???
- completionEvent->schedule(pkt->req->responseTime - pkt->req->requestTime);
- completionEvent == NULL;
+ // some kind of selction between access methods
+ // more work is going to have to be done to make
+ // switching actually work
+
+ System::MemoryMode state = sys->getMemoryMode();
+ if (state == System::Timing) {
+ DPRINTF(DMA, "Attempting to send Packet %#x with addr: %#x\n",
+ pkt, pkt->getAddr());
+ if (transmitList.size() || !sendTiming(pkt)) {
+ if (front)
+ transmitList.push_front(pkt);
+ else
+ transmitList.push_back(pkt);
+ DPRINTF(DMA, "-- Failed: queued\n");
+ } else {
+ DPRINTF(DMA, "-- Done\n");
+ }
+ } else if (state == System::Atomic) {
+ Tick lat;
+ lat = sendAtomic(pkt);
+ assert(pkt->senderState);
+ DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState);
+ assert(state);
+
+ state->numBytes += pkt->req->getSize();
+ if (state->totBytes == state->numBytes) {
+ state->completionEvent->schedule(curTick + lat);
+ delete state;
+ delete pkt->req;
+ }
+ pendingCount--;
+ assert(pendingCount >= 0);
+ delete pkt;
+
+ if (pendingCount == 0 && drainEvent) {
+ drainEvent->process();
+ drainEvent = NULL;
+ }
+
} else
panic("Unknown memory command state.");
- */
}
DmaDevice::~DmaDevice()
diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh
index 195ca0fb7..fa3f98247 100644
--- a/src/dev/io_device.hh
+++ b/src/dev/io_device.hh
@@ -60,9 +60,9 @@ class PioPort : public Port
/** The device that this port serves. */
PioDevice *device;
- /** The platform that device/port are in. This is used to select which mode
+ /** The system that device/port are in. This is used to select which mode
* we are currently operating in. */
- Platform *platform;
+ System *sys;
/** A list of outgoing timing response packets that haven't been serviced
* yet. */
@@ -82,6 +82,8 @@ class PioPort : public Port
virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop);
+ void resendNacked(Packet *pkt);
+
/**
* This class is used to implemented sendTiming() with a delay. When a delay
* is requested a new event is created. When the event time expires it
@@ -104,55 +106,72 @@ class PioPort : public Port
friend class PioPort;
};
+ /** Number of timing requests that are emulating the device timing before
+ * attempting to end up on the bus.
+ */
+ int outTiming;
+
+ /** If we need to drain, keep the drain event around until we're done
+ * here.*/
+ Event *drainEvent;
+
/** Schedule a sendTiming() event to be called in the future. */
void sendTiming(Packet *pkt, Tick time)
- { new PioPort::SendEvent(this, pkt, time); }
+ { outTiming++; new PioPort::SendEvent(this, pkt, time); }
/** This function is notification that the device should attempt to send a
* packet again. */
virtual void recvRetry();
public:
- PioPort(PioDevice *dev, Platform *p);
+ PioPort(PioDevice *dev, System *s, std::string pname = "-pioport");
+
+ unsigned int drain(Event *de);
friend class PioPort::SendEvent;
};
-struct DmaReqState : public Packet::SenderState
+class DmaPort : public Port
{
- /** Event to call on the device when this transaction (all packets)
- * complete. */
- Event *completionEvent;
+ protected:
+ struct DmaReqState : public Packet::SenderState
+ {
+ /** Event to call on the device when this transaction (all packets)
+ * complete. */
+ Event *completionEvent;
- /** Where we came from for some sanity checking. */
- Port *outPort;
+ /** Where we came from for some sanity checking. */
+ Port *outPort;
- /** Total number of bytes that this transaction involves. */
- Addr totBytes;
+ /** Total number of bytes that this transaction involves. */
+ Addr totBytes;
- /** Number of bytes that have been acked for this transaction. */
- Addr numBytes;
+ /** Number of bytes that have been acked for this transaction. */
+ Addr numBytes;
- bool final;
- DmaReqState(Event *ce, Port *p, Addr tb)
- : completionEvent(ce), outPort(p), totBytes(tb), numBytes(0)
- {}
-};
+ DmaReqState(Event *ce, Port *p, Addr tb)
+ : completionEvent(ce), outPort(p), totBytes(tb), numBytes(0)
+ {}
+ };
-class DmaPort : public Port
-{
- protected:
DmaDevice *device;
std::list<Packet*> transmitList;
- /** The platform that device/port are in. This is used to select which mode
+ /** The system that device/port are in. This is used to select which mode
* we are currently operating in. */
- Platform *platform;
+ System *sys;
/** Number of outstanding packets the dma port has. */
int pendingCount;
+ /** If a dmaAction is in progress. */
+ int actionInProgress;
+
+ /** If we need to drain, keep the drain event around until we're done
+ * here.*/
+ Event *drainEvent;
+
virtual bool recvTiming(Packet *pkt);
virtual Tick recvAtomic(Packet *pkt)
{ panic("dma port shouldn't be used for pio access."); }
@@ -170,13 +189,14 @@ class DmaPort : public Port
void sendDma(Packet *pkt, bool front = false);
public:
- DmaPort(DmaDevice *dev, Platform *p);
+ DmaPort(DmaDevice *dev, System *s);
void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
uint8_t *data = NULL);
bool dmaPending() { return pendingCount > 0; }
+ unsigned int drain(Event *de);
};
/**
@@ -195,6 +215,8 @@ class PioDevice : public MemObject
* transaction we should perform. */
Platform *platform;
+ System *sys;
+
/** The pioPort that handles the requests for us and provides us requests
* that it sees. */
PioPort *pioPort;
@@ -239,20 +261,22 @@ class PioDevice : public MemObject
const Params *params() const { return _params; }
PioDevice(Params *p)
- : MemObject(p->name), platform(p->platform), pioPort(NULL),
- _params(p)
+ : MemObject(p->name), platform(p->platform), sys(p->system),
+ pioPort(NULL), _params(p)
{}
virtual ~PioDevice();
virtual void init();
- virtual Port *getPort(const std::string &if_name)
+ virtual unsigned int drain(Event *de);
+
+ virtual Port *getPort(const std::string &if_name, int idx = -1)
{
if (if_name == "pio") {
if (pioPort != NULL)
panic("pio port already connected to.");
- pioPort = new PioPort(this, params()->platform);
+ pioPort = new PioPort(this, sys);
return pioPort;
} else
return NULL;
@@ -309,17 +333,19 @@ class DmaDevice : public PioDevice
bool dmaPending() { return dmaPort->dmaPending(); }
- virtual Port *getPort(const std::string &if_name)
+ virtual unsigned int drain(Event *de);
+
+ virtual Port *getPort(const std::string &if_name, int idx = -1)
{
if (if_name == "pio") {
if (pioPort != NULL)
panic("pio port already connected to.");
- pioPort = new PioPort(this, params()->platform);
+ pioPort = new PioPort(this, sys);
return pioPort;
} else if (if_name == "dma") {
if (dmaPort != NULL)
panic("dma port already connected to.");
- dmaPort = new DmaPort(this, params()->platform);
+ dmaPort = new DmaPort(this, sys);
return dmaPort;
} else
return NULL;
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index decffaf73..bf2279d93 100644
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -25,7 +25,8 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Lisa Hsu
+ * Authors: Nathan Binkert
+ * Lisa Hsu
*/
/** @file
@@ -464,11 +465,12 @@ NSGigE::regStats()
/**
* This is to write to the PCI general configuration registers
*/
-void
-NSGigE::writeConfig(int offset, const uint16_t data)
+Tick
+NSGigE::writeConfig(Packet *pkt)
{
+ int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC)
- PciDev::writeConfig(offset, data);
+ PciDev::writeConfig(pkt);
else
panic("Device specific PCI config space not implemented!\n");
@@ -483,6 +485,8 @@ NSGigE::writeConfig(int offset, const uint16_t data)
ioEnable = false;
break;
}
+ pkt->result = Packet::Success;
+ return configDelay;
}
/**
@@ -507,14 +511,7 @@ NSGigE::read(Packet *pkt)
if (daddr > LAST && daddr <= RESERVED) {
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
- if (pkt->getSize() == sizeof(uint8_t))
- readConfig(daddr & 0xff, pkt->getPtr<uint8_t>());
- if (pkt->getSize() == sizeof(uint16_t))
- readConfig(daddr & 0xff, pkt->getPtr<uint16_t>());
- if (pkt->getSize() == sizeof(uint32_t))
- readConfig(daddr & 0xff, pkt->getPtr<uint32_t>());
- pkt->result = Packet::Success;
- return pioDelay;
+ return readConfig(pkt);
} else if (daddr >= MIB_START && daddr <= MIB_END) {
// don't implement all the MIB's. hopefully the kernel
// doesn't actually DEPEND upon their values
@@ -732,14 +729,7 @@ NSGigE::write(Packet *pkt)
if (daddr > LAST && daddr <= RESERVED) {
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
- if (pkt->getSize() == sizeof(uint8_t))
- writeConfig(daddr & 0xff, pkt->get<uint8_t>());
- if (pkt->getSize() == sizeof(uint16_t))
- writeConfig(daddr & 0xff, pkt->get<uint16_t>());
- if (pkt->getSize() == sizeof(uint32_t))
- writeConfig(daddr & 0xff, pkt->get<uint32_t>());
- pkt->result = Packet::Success;
- return pioDelay;
+ return writeConfig(pkt);
} else if (daddr > 0x3FC)
panic("Something is messed up!\n");
@@ -1387,7 +1377,7 @@ NSGigE::doRxDmaRead()
assert(rxDmaState == dmaIdle || rxDmaState == dmaReadWaiting);
rxDmaState = dmaReading;
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
rxDmaState = dmaReadWaiting;
else
dmaRead(rxDmaAddr, rxDmaLen, &rxDmaReadEvent, (uint8_t*)rxDmaData);
@@ -1418,7 +1408,7 @@ NSGigE::doRxDmaWrite()
assert(rxDmaState == dmaIdle || rxDmaState == dmaWriteWaiting);
rxDmaState = dmaWriting;
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
rxDmaState = dmaWriteWaiting;
else
dmaWrite(rxDmaAddr, rxDmaLen, &rxDmaWriteEvent, (uint8_t*)rxDmaData);
@@ -1836,7 +1826,7 @@ NSGigE::doTxDmaRead()
assert(txDmaState == dmaIdle || txDmaState == dmaReadWaiting);
txDmaState = dmaReading;
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
txDmaState = dmaReadWaiting;
else
dmaRead(txDmaAddr, txDmaLen, &txDmaReadEvent, (uint8_t*)txDmaData);
@@ -1867,7 +1857,7 @@ NSGigE::doTxDmaWrite()
assert(txDmaState == dmaIdle || txDmaState == dmaWriteWaiting);
txDmaState = dmaWriting;
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
txDmaState = dmaWriteWaiting;
else
dmaWrite(txDmaAddr, txDmaLen, &txDmaWriteEvent, (uint8_t*)txDmaData);
@@ -2416,6 +2406,20 @@ NSGigE::recvPacket(EthPacketPtr packet)
return true;
}
+
+void
+NSGigE::resume()
+{
+ SimObject::resume();
+
+ // During drain we could have left the state machines in a waiting state and
+ // they wouldn't get out until some other event occured to kick them.
+ // This way they'll get out immediately
+ txKick();
+ rxKick();
+}
+
+
//=====================================================================
//
//
@@ -2806,7 +2810,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
SimObjectParam<System *> system;
SimObjectParam<Platform *> platform;
- SimObjectParam<PciConfigAll *> configspace;
SimObjectParam<PciConfigData *> configdata;
Param<uint32_t> pci_bus;
Param<uint32_t> pci_dev;
@@ -2840,7 +2843,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(system, "System pointer"),
INIT_PARAM(platform, "Platform pointer"),
- INIT_PARAM(configspace, "PCI Configspace"),
INIT_PARAM(configdata, "PCI Config data"),
INIT_PARAM(pci_bus, "PCI bus ID"),
INIT_PARAM(pci_dev, "PCI device number"),
@@ -2878,7 +2880,6 @@ CREATE_SIM_OBJECT(NSGigE)
params->name = getInstanceName();
params->platform = platform;
params->system = system;
- params->configSpace = configspace;
params->configData = configdata;
params->busNum = pci_bus;
params->deviceNum = pci_dev;
diff --git a/src/dev/ns_gige.hh b/src/dev/ns_gige.hh
index 2de11c951..080c0b1f3 100644
--- a/src/dev/ns_gige.hh
+++ b/src/dev/ns_gige.hh
@@ -25,7 +25,8 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Lisa Hsu
+ * Authors: Nathan Binkert
+ * Lisa Hsu
*/
/** @file
@@ -113,7 +114,6 @@ struct dp_rom {
class NSGigEInt;
class Packet;
-class PciConfigAll;
/**
* NS DP83820 Ethernet device model
@@ -375,7 +375,7 @@ class NSGigE : public PciDev
~NSGigE();
const Params *params() const { return (const Params *)_params; }
- virtual void writeConfig(int offset, const uint16_t data);
+ virtual Tick writeConfig(Packet *pkt);
virtual Tick read(Packet *pkt);
virtual Tick write(Packet *pkt);
@@ -391,6 +391,8 @@ class NSGigE : public PciDev
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
+ virtual void resume();
+
public:
void regStats();
diff --git a/src/dev/pciconfigall.cc b/src/dev/pciconfigall.cc
index 785774ff4..68013eab8 100644
--- a/src/dev/pciconfigall.cc
+++ b/src/dev/pciconfigall.cc
@@ -33,14 +33,8 @@
* PCI Configspace implementation
*/
-#include <deque>
-#include <string>
-#include <vector>
-#include <bitset>
-
#include "base/trace.hh"
#include "dev/pciconfigall.hh"
-#include "dev/pcidev.hh"
#include "dev/pcireg.h"
#include "dev/platform.hh"
#include "mem/packet.hh"
@@ -50,151 +44,61 @@
using namespace std;
PciConfigAll::PciConfigAll(Params *p)
- : BasicPioDevice(p)
+ : PioDevice(p)
{
- pioSize = 0xffffff;
-
- // Set backpointer for pci config. Really the config stuff should be able to
- // automagically do this
- p->platform->pciconfig = this;
-
- // Make all the pointers to devices null
- for(int x=0; x < MAX_PCI_DEV; x++)
- for(int y=0; y < MAX_PCI_FUNC; y++)
- devices[x][y] = NULL;
+ pioAddr = p->platform->calcConfigAddr(params()->bus,0,0);
}
-// If two interrupts share the same line largely bad things will happen.
-// Since we don't track how many times an interrupt was set and correspondingly
-// cleared two devices on the same interrupt line and assert and deassert each
-// others interrupt "line". Interrupts will not work correctly.
-void
-PciConfigAll::startup()
-{
- bitset<256> intLines;
- PciDev *tempDev;
- uint8_t intline;
-
- for (int x = 0; x < MAX_PCI_DEV; x++) {
- for (int y = 0; y < MAX_PCI_FUNC; y++) {
- if (devices[x][y] != NULL) {
- tempDev = devices[x][y];
- intline = tempDev->interruptLine();
- if (intLines.test(intline))
- warn("Interrupt line %#X is used multiple times"
- "(You probably want to fix this).\n", (uint32_t)intline);
- else
- intLines.set(intline);
- } // devices != NULL
- } // PCI_FUNC
- } // PCI_DEV
-
-}
Tick
PciConfigAll::read(Packet *pkt)
{
assert(pkt->result == Packet::Unknown);
- assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
-
- Addr daddr = pkt->getAddr() - pioAddr;
- int device = (daddr >> 11) & 0x1F;
- int func = (daddr >> 8) & 0x7;
- int reg = daddr & 0xFF;
pkt->allocate();
- DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", pkt->getAddr(), daddr,
+ DPRINTF(PciConfigAll, "read va=%#x size=%d\n", pkt->getAddr(),
pkt->getSize());
switch (pkt->getSize()) {
case sizeof(uint32_t):
- if (devices[device][func] == NULL)
- pkt->set<uint32_t>(0xFFFFFFFF);
- else
- devices[device][func]->readConfig(reg, pkt->getPtr<uint32_t>());
+ pkt->set<uint32_t>(0xFFFFFFFF);
break;
case sizeof(uint16_t):
- if (devices[device][func] == NULL)
- pkt->set<uint16_t>(0xFFFF);
- else
- devices[device][func]->readConfig(reg, pkt->getPtr<uint16_t>());
+ pkt->set<uint16_t>(0xFFFF);
break;
case sizeof(uint8_t):
- if (devices[device][func] == NULL)
- pkt->set<uint8_t>(0xFF);
- else
- devices[device][func]->readConfig(reg, pkt->getPtr<uint8_t>());
+ pkt->set<uint8_t>(0xFF);
break;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
pkt->result = Packet::Success;
- return pioDelay;
+ return params()->pio_delay;
}
Tick
PciConfigAll::write(Packet *pkt)
{
assert(pkt->result == Packet::Unknown);
- assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
- assert(pkt->getSize() == sizeof(uint8_t) || pkt->getSize() == sizeof(uint16_t) ||
- pkt->getSize() == sizeof(uint32_t));
- Addr daddr = pkt->getAddr() - pioAddr;
-
- int device = (daddr >> 11) & 0x1F;
- int func = (daddr >> 8) & 0x7;
- int reg = daddr & 0xFF;
-
- if (devices[device][func] == NULL)
- panic("Attempting to write to config space on non-existant device\n");
-
- DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
- pkt->getAddr(), pkt->getSize(), pkt->get<uint32_t>());
-
- switch (pkt->getSize()) {
- case sizeof(uint8_t):
- devices[device][func]->writeConfig(reg, pkt->get<uint8_t>());
- break;
- case sizeof(uint16_t):
- devices[device][func]->writeConfig(reg, pkt->get<uint16_t>());
- break;
- case sizeof(uint32_t):
- devices[device][func]->writeConfig(reg, pkt->get<uint32_t>());
- break;
- default:
- panic("invalid pci config write size\n");
- }
- pkt->result = Packet::Success;
- return pioDelay;
+ panic("Attempting to write to config space on non-existant device\n");
}
void
-PciConfigAll::serialize(std::ostream &os)
+PciConfigAll::addressRanges(AddrRangeList &range_list)
{
- /*
- * There is no state associated with this object that requires
- * serialization. The only real state are the device pointers
- * which are all setup by the constructor of the PciDev class
- */
+ range_list.clear();
+ range_list.push_back(RangeSize(pioAddr, params()->size));
}
-void
-PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
-{
- /*
- * There is no state associated with this object that requires
- * serialization. The only real state are the device pointers
- * which are all setup by the constructor of the PciDev class
- */
-}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
- Param<Addr> pio_addr;
Param<Tick> pio_latency;
+ Param<int> bus;
+ Param<Addr> size;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
@@ -202,8 +106,9 @@ END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
- INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
+ INIT_PARAM(bus, "Bus that this object handles config space for"),
+ INIT_PARAM(size, "The size of config space"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object")
@@ -211,11 +116,13 @@ END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
CREATE_SIM_OBJECT(PciConfigAll)
{
- BasicPioDevice::Params *p = new BasicPioDevice::Params;
- p->pio_addr = pio_addr;
+ PciConfigAll::Params *p = new PciConfigAll::Params;
p->pio_delay = pio_latency;
p->platform = platform;
p->system = system;
+ p->bus = bus;
+ p->size = size;
+
return new PciConfigAll(p);
}
diff --git a/src/dev/pciconfigall.hh b/src/dev/pciconfigall.hh
index e60fd949b..07eaf8112 100644
--- a/src/dev/pciconfigall.hh
+++ b/src/dev/pciconfigall.hh
@@ -42,11 +42,6 @@
#include "dev/io_device.hh"
-static const uint32_t MAX_PCI_DEV = 32;
-static const uint32_t MAX_PCI_FUNC = 8;
-
-class PciDev;
-
/**
* PCI Config Space
* All of PCI config space needs to return -1 on Tsunami, except
@@ -54,16 +49,17 @@ class PciDev;
* space and passes the requests on to TsunamiPCIDev devices as
* appropriate.
*/
-class PciConfigAll : public BasicPioDevice
+class PciConfigAll : public PioDevice
{
- private:
- /**
- * Pointers to all the devices that are registered with this
- * particular config space.
- */
- PciDev* devices[MAX_PCI_DEV][MAX_PCI_FUNC];
-
public:
+ struct Params : public PioDevice::Params
+ {
+ Tick pio_delay;
+ Addr size;
+ int bus;
+ };
+ const Params *params() const { return (const Params *)_params; }
+
/**
* Constructor for PCIConfigAll
* @param p parameters structure
@@ -71,28 +67,10 @@ class PciConfigAll : public BasicPioDevice
PciConfigAll(Params *p);
/**
- * Check if a device exists.
- * @param pcidev PCI device to check
- * @param pcifunc PCI function to check
- * @return true if device exists, false otherwise
- */
- bool deviceExists(uint32_t pcidev, uint32_t pcifunc)
- { return devices[pcidev][pcifunc] != NULL ? true : false; }
-
- /**
- * Registers a device with the config space object.
- * @param pcidev PCI device to register
- * @param pcifunc PCI function to register
- * @param device device to register
- */
- void registerDevice(uint8_t pcidev, uint8_t pcifunc, PciDev *device)
- { devices[pcidev][pcifunc] = device; }
-
- /**
* Read something in PCI config space. If the device does not exist
* -1 is returned, if the device does exist its PciDev::ReadConfig (or the
* virtual function that overrides) it is called.
- * @param pkt Contains the address of the field to read.
+ * @param pkt Contains information about the read operation
* @return Amount of time to do the read
*/
virtual Tick read(Packet *pkt);
@@ -101,31 +79,17 @@ class PciConfigAll : public BasicPioDevice
* Write to PCI config spcae. If the device does not exit the simulator
* panics. If it does it is passed on the PciDev::WriteConfig (or the virtual
* function that overrides it).
- * @param req Contains the address to write to.
- * @param data The data to write.
- * @return The fault condition of the access.
+ * @param pkt Contains information about the write operation
+ * @return Amount of time to do the read
*/
virtual Tick write(Packet *pkt);
- /**
- * Start up function to check if more than one person is using an interrupt line
- * and print a warning if such a case exists
- */
- virtual void startup();
+ void addressRanges(AddrRangeList &range_list);
- /**
- * Serialize this object to the given output stream.
- * @param os The stream to serialize to.
- */
- virtual void serialize(std::ostream &os);
+ private:
+ Addr pioAddr;
- /**
- * Reconstruct the state of this object from a checkpoint.
- * @param cp The checkpoint use.
- * @param section The section name of this object
- */
- virtual void unserialize(Checkpoint *cp, const std::string &section);
};
#endif // __PCICONFIGALL_HH__
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index f8db2efbc..e81e0d1ee 100644
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -53,201 +53,268 @@
using namespace std;
-PciDev::PciDev(Params *p)
- : DmaDevice(p), plat(p->platform), configData(p->configData),
- pioDelay(p->pio_delay)
-{
- // copy the config data from the PciConfigData object
- if (configData) {
- memcpy(config.data, configData->config.data, sizeof(config.data));
- memcpy(BARSize, configData->BARSize, sizeof(BARSize));
- memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs));
- } else
- panic("NULL pointer to configuration data");
- // Setup pointer in config space to point to this entry
- if (p->configSpace->deviceExists(p->deviceNum, p->functionNum))
- panic("Two PCI devices occuping same dev: %#x func: %#x",
- p->deviceNum, p->functionNum);
- else
- p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
-}
-
-void
-PciDev::readConfig(int offset, uint8_t *data)
+PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
+ int funcid, Platform *p)
+ : PioPort(dev,p->system,"-pciconf"), device(dev), platform(p),
+ busId(busid), deviceId(devid), functionId(funcid)
{
- if (offset >= PCI_DEVICE_SPECIFIC)
- panic("Device specific PCI config space not implemented!\n");
+ configAddr = platform->calcConfigAddr(busId, deviceId, functionId);
+}
- *data = config.data[offset];
- DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x 1 bytes: data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, *data);
+Tick
+PciDev::PciConfigPort::recvAtomic(Packet *pkt)
+{
+ assert(pkt->result == Packet::Unknown);
+ assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr +
+ PCI_CONFIG_SIZE);
+ return device->recvConfig(pkt);
}
void
-PciDev::addressRanges(AddrRangeList &range_list)
+PciDev::PciConfigPort::recvFunctional(Packet *pkt)
{
- int x = 0;
- range_list.clear();
- for (x = 0; x < 6; x++)
- if (BARAddrs[x] != 0)
- range_list.push_back(RangeSize(BARAddrs[x],BARSize[x]));
+ assert(pkt->result == Packet::Unknown);
+ assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr +
+ PCI_CONFIG_SIZE);
+ device->recvConfig(pkt);
}
void
-PciDev::readConfig(int offset, uint16_t *data)
+PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
{
- if (offset >= PCI_DEVICE_SPECIFIC)
- panic("Device specific PCI config space not implemented!\n");
+ snoop.clear();
+ resp.push_back(RangeSize(configAddr, PCI_CONFIG_SIZE+1));
+}
- *data = *(uint16_t*)&config.data[offset];
- DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x 2 bytes: data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, *data);
+bool
+PciDev::PciConfigPort::recvTiming(Packet *pkt)
+{
+ if (pkt->result == Packet::Nacked) {
+ resendNacked(pkt);
+ } else {
+ assert(pkt->result == Packet::Unknown);
+ assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr +
+ PCI_CONFIG_SIZE);
+ Tick latency = device->recvConfig(pkt);
+ // turn packet around to go back to requester
+ pkt->makeTimingResponse();
+ sendTiming(pkt, latency);
+ }
+ return true;
}
-void
-PciDev::readConfig(int offset, uint32_t *data)
+PciDev::PciDev(Params *p)
+ : DmaDevice(p), plat(p->platform), configData(p->configData),
+ pioDelay(p->pio_delay), configDelay(p->config_delay),
+ configPort(NULL)
{
- if (offset >= PCI_DEVICE_SPECIFIC)
- panic("Device specific PCI config space not implemented!\n");
+ // copy the config data from the PciConfigData object
+ if (configData) {
+ memcpy(config.data, configData->config.data, sizeof(config.data));
+ memcpy(BARSize, configData->BARSize, sizeof(BARSize));
+ memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs));
+ } else
+ panic("NULL pointer to configuration data");
- *data = *(uint32_t*)&config.data[offset];
+ plat->registerPciDevice(0, p->deviceNum, p->functionNum,
+ letoh(configData->config.interruptLine));
+}
- DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x 4 bytes: data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, *data);
+void
+PciDev::init()
+{
+ if (!configPort)
+ panic("pci config port not connected to anything!");
+ configPort->sendStatusChange(Port::RangeChange);
+ PioDevice::init();
}
+unsigned int
+PciDev::drain(Event *de)
+{
+ unsigned int count;
+ count = pioPort->drain(de) + dmaPort->drain(de) + configPort->drain(de);
+ if (count)
+ changeState(Draining);
+ else
+ changeState(Drained);
+ return count;
+}
-void
-PciDev::writeConfig(int offset, const uint8_t data)
+Tick
+PciDev::readConfig(Packet *pkt)
{
+ int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset >= PCI_DEVICE_SPECIFIC)
panic("Device specific PCI config space not implemented!\n");
- DPRINTF(PCIDEV,
- "write device: %#x function: %#x reg: %#x size: 1 data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, data);
-
- switch (offset) {
- case PCI0_INTERRUPT_LINE:
- config.interruptLine = data;
- case PCI_CACHE_LINE_SIZE:
- config.cacheLineSize = data;
- case PCI_LATENCY_TIMER:
- config.latencyTimer = data;
+ pkt->allocate();
+
+ switch (pkt->getSize()) {
+ case sizeof(uint8_t):
+ pkt->set<uint8_t>(config.data[offset]);
+ DPRINTF(PCIDEV,
+ "read device: %#x function: %#x register: %#x 1 bytes: data: %#x\n",
+ params()->deviceNum, params()->functionNum, offset,
+ (uint32_t)pkt->get<uint8_t>());
break;
- /* Do nothing for these read-only registers */
- case PCI0_INTERRUPT_PIN:
- case PCI0_MINIMUM_GRANT:
- case PCI0_MAXIMUM_LATENCY:
- case PCI_CLASS_CODE:
- case PCI_REVISION_ID:
+ case sizeof(uint16_t):
+ pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
+ DPRINTF(PCIDEV,
+ "read device: %#x function: %#x register: %#x 2 bytes: data: %#x\n",
+ params()->deviceNum, params()->functionNum, offset,
+ (uint32_t)pkt->get<uint16_t>());
+ break;
+ case sizeof(uint32_t):
+ pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
+ DPRINTF(PCIDEV,
+ "read device: %#x function: %#x register: %#x 4 bytes: data: %#x\n",
+ params()->deviceNum, params()->functionNum, offset,
+ (uint32_t)pkt->get<uint32_t>());
break;
default:
- panic("writing to a read only register");
+ panic("invalid access size(?) for PCI configspace!\n");
}
+ pkt->result = Packet::Success;
+ return configDelay;
+
}
void
-PciDev::writeConfig(int offset, const uint16_t data)
+PciDev::addressRanges(AddrRangeList &range_list)
{
- if (offset >= PCI_DEVICE_SPECIFIC)
- panic("Device specific PCI config space not implemented!\n");
-
- DPRINTF(PCIDEV,
- "write device: %#x function: %#x reg: %#x size: 2 data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, data);
-
- switch (offset) {
- case PCI_COMMAND:
- config.command = data;
- case PCI_STATUS:
- config.status = data;
- case PCI_CACHE_LINE_SIZE:
- config.cacheLineSize = data;
- break;
- default:
- panic("writing to a read only register");
- }
+ int x = 0;
+ range_list.clear();
+ for (x = 0; x < 6; x++)
+ if (BARAddrs[x] != 0)
+ range_list.push_back(RangeSize(BARAddrs[x],BARSize[x]));
}
-
-void
-PciDev::writeConfig(int offset, const uint32_t data)
+Tick
+PciDev::writeConfig(Packet *pkt)
{
+ int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset >= PCI_DEVICE_SPECIFIC)
panic("Device specific PCI config space not implemented!\n");
- DPRINTF(PCIDEV,
- "write device: %#x function: %#x reg: %#x size: 4 data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, data);
-
- switch (offset) {
- case PCI0_BASE_ADDR0:
- case PCI0_BASE_ADDR1:
- case PCI0_BASE_ADDR2:
- case PCI0_BASE_ADDR3:
- case PCI0_BASE_ADDR4:
- case PCI0_BASE_ADDR5:
-
- uint32_t barnum, bar_mask;
- Addr base_addr, base_size, space_base;
-
- barnum = BAR_NUMBER(offset);
-
- if (BAR_IO_SPACE(letoh(config.baseAddr[barnum]))) {
- bar_mask = BAR_IO_MASK;
- space_base = TSUNAMI_PCI0_IO;
- } else {
- bar_mask = BAR_MEM_MASK;
- space_base = TSUNAMI_PCI0_MEMORY;
+ switch (pkt->getSize()) {
+ case sizeof(uint8_t):
+ switch (offset) {
+ case PCI0_INTERRUPT_LINE:
+ config.interruptLine = pkt->get<uint8_t>();
+ case PCI_CACHE_LINE_SIZE:
+ config.cacheLineSize = pkt->get<uint8_t>();
+ case PCI_LATENCY_TIMER:
+ config.latencyTimer = pkt->get<uint8_t>();
+ break;
+ /* Do nothing for these read-only registers */
+ case PCI0_INTERRUPT_PIN:
+ case PCI0_MINIMUM_GRANT:
+ case PCI0_MAXIMUM_LATENCY:
+ case PCI_CLASS_CODE:
+ case PCI_REVISION_ID:
+ break;
+ default:
+ panic("writing to a read only register");
}
+ DPRINTF(PCIDEV,
+ "write device: %#x function: %#x register: %#x 1 bytes: data: %#x\n",
+ params()->deviceNum, params()->functionNum, offset,
+ (uint32_t)pkt->get<uint8_t>());
+ break;
+ case sizeof(uint16_t):
+ switch (offset) {
+ case PCI_COMMAND:
+ config.command = pkt->get<uint8_t>();
+ case PCI_STATUS:
+ config.status = pkt->get<uint8_t>();
+ case PCI_CACHE_LINE_SIZE:
+ config.cacheLineSize = pkt->get<uint8_t>();
+ break;
+ default:
+ panic("writing to a read only register");
+ }
+ DPRINTF(PCIDEV,
+ "write device: %#x function: %#x register: %#x 2 bytes: data: %#x\n",
+ params()->deviceNum, params()->functionNum, offset,
+ (uint32_t)pkt->get<uint16_t>());
+ break;
+ case sizeof(uint32_t):
+ switch (offset) {
+ case PCI0_BASE_ADDR0:
+ case PCI0_BASE_ADDR1:
+ case PCI0_BASE_ADDR2:
+ case PCI0_BASE_ADDR3:
+ case PCI0_BASE_ADDR4:
+ case PCI0_BASE_ADDR5:
+
+ uint32_t barnum, bar_mask;
+ Addr base_addr, base_size, space_base;
+
+ barnum = BAR_NUMBER(offset);
+
+ if (BAR_IO_SPACE(letoh(config.baseAddr[barnum]))) {
+ bar_mask = BAR_IO_MASK;
+ space_base = TSUNAMI_PCI0_IO;
+ } else {
+ bar_mask = BAR_MEM_MASK;
+ space_base = TSUNAMI_PCI0_MEMORY;
+ }
- // Writing 0xffffffff to a BAR tells the card to set the
- // value of the bar to size of memory it needs
- if (letoh(data) == 0xffffffff) {
- // This is I/O Space, bottom two bits are read only
-
- config.baseAddr[barnum] = letoh(
- (~(BARSize[barnum] - 1) & ~bar_mask) |
+ // Writing 0xffffffff to a BAR tells the card to set the
+ // value of the bar to size of memory it needs
+ if (letoh(pkt->get<uint32_t>()) == 0xffffffff) {
+ // This is I/O Space, bottom two bits are read only
+
+ config.baseAddr[barnum] = letoh(
+ (~(BARSize[barnum] - 1) & ~bar_mask) |
+ (letoh(config.baseAddr[barnum]) & bar_mask));
+ } else {
+ config.baseAddr[barnum] = letoh(
+ (letoh(pkt->get<uint32_t>()) & ~bar_mask) |
(letoh(config.baseAddr[barnum]) & bar_mask));
- } else {
- config.baseAddr[barnum] = letoh(
- (letoh(data) & ~bar_mask) |
- (letoh(config.baseAddr[barnum]) & bar_mask));
- if (letoh(config.baseAddr[barnum]) & ~bar_mask) {
- base_addr = (letoh(data) & ~bar_mask) + space_base;
- base_size = BARSize[barnum];
- BARAddrs[barnum] = base_addr;
+ if (letoh(config.baseAddr[barnum]) & ~bar_mask) {
+ base_addr = (letoh(pkt->get<uint32_t>()) & ~bar_mask) + space_base;
+ base_size = BARSize[barnum];
+ BARAddrs[barnum] = base_addr;
- pioPort->sendStatusChange(Port::RangeChange);
+ pioPort->sendStatusChange(Port::RangeChange);
+ }
}
+ break;
+
+ case PCI0_ROM_BASE_ADDR:
+ if (letoh(pkt->get<uint32_t>()) == 0xfffffffe)
+ config.expansionROM = htole((uint32_t)0xffffffff);
+ else
+ config.expansionROM = pkt->get<uint32_t>();
+ break;
+
+ case PCI_COMMAND:
+ // This could also clear some of the error bits in the Status
+ // register. However they should never get set, so lets ignore
+ // it for now
+ config.command = pkt->get<uint32_t>();
+ break;
+
+ default:
+ DPRINTF(PCIDEV, "Writing to a read only register");
}
+ DPRINTF(PCIDEV,
+ "write device: %#x function: %#x register: %#x 4 bytes: data: %#x\n",
+ params()->deviceNum, params()->functionNum, offset,
+ (uint32_t)pkt->get<uint32_t>());
break;
-
- case PCI0_ROM_BASE_ADDR:
- if (letoh(data) == 0xfffffffe)
- config.expansionROM = htole((uint32_t)0xffffffff);
- else
- config.expansionROM = data;
- break;
-
- case PCI_COMMAND:
- // This could also clear some of the error bits in the Status
- // register. However they should never get set, so lets ignore
- // it for now
- config.command = data;
- break;
-
default:
- DPRINTF(PCIDEV, "Writing to a read only register");
+ panic("invalid access size(?) for PCI configspace!\n");
}
+ pkt->result = Packet::Success;
+ return configDelay;
+
}
void
diff --git a/src/dev/pcidev.hh b/src/dev/pcidev.hh
index 92786427b..847fb07d0 100644
--- a/src/dev/pcidev.hh
+++ b/src/dev/pcidev.hh
@@ -47,8 +47,6 @@
#define BAR_IO_SPACE(x) ((x) & BAR_IO_SPACE_BIT)
#define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2);
-class PciConfigAll;
-
/**
* This class encapulates the first 64 bytes of a singles PCI
@@ -78,24 +76,43 @@ class PciConfigData : public SimObject
Addr BARAddrs[6];
};
+
/**
* PCI device, base implemnation is only config space.
- * Each device is connected to a PCIConfigSpace device
- * which returns -1 for everything but the pcidevs that
- * register with it. This object registers with the PCIConfig space
- * object.
*/
class PciDev : public DmaDevice
{
- public:
- struct Params : public ::PioDevice::Params
+ class PciConfigPort : public PioPort
{
- /**
- * A pointer to the configspace all object that calls us when
- * a read comes to this particular device/function.
- */
- PciConfigAll *configSpace;
+ protected:
+ PciDev *device;
+
+ virtual bool recvTiming(Packet *pkt);
+
+ virtual Tick recvAtomic(Packet *pkt);
+
+ virtual void recvFunctional(Packet *pkt) ;
+
+ virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop);
+
+ Platform *platform;
+
+ int busId;
+ int deviceId;
+ int functionId;
+
+ Addr configAddr;
+
+ public:
+ PciConfigPort(PciDev *dev, int busid, int devid, int funcid,
+ Platform *p);
+ friend class PioPort::SendEvent;
+ };
+
+ public:
+ struct Params : public PioDevice::Params
+ {
/**
* A pointer to the object that contains the first 64 bytes of
* config space
@@ -113,6 +130,9 @@ class PciDev : public DmaDevice
/** The latency for pio accesses. */
Tick pio_delay;
+
+ /** The latency for a config access. */
+ Tick config_delay;
};
public:
@@ -164,6 +184,25 @@ class PciDev : public DmaDevice
Platform *plat;
PciConfigData *configData;
Tick pioDelay;
+ Tick configDelay;
+ PciConfigPort *configPort;
+
+ /**
+ * Write to the PCI config space data that is stored locally. This may be
+ * overridden by the device but at some point it will eventually call this
+ * for normal operations that it does not need to override.
+ * @param pkt packet containing the write the offset into config space
+ */
+ virtual Tick writeConfig(Packet *pkt);
+
+
+ /**
+ * Read from the PCI config space data that is stored locally. This may be
+ * overridden by the device but at some point it will eventually call this
+ * for normal operations that it does not need to override.
+ * @param pkt packet containing the write the offset into config space
+ */
+ virtual Tick readConfig(Packet *pkt);
public:
Addr pciToDma(Addr pciAddr) const
@@ -171,21 +210,25 @@ class PciDev : public DmaDevice
void
intrPost()
- { plat->postPciInt(configData->config.interruptLine); }
+ { plat->postPciInt(letoh(configData->config.interruptLine)); }
void
intrClear()
- { plat->clearPciInt(configData->config.interruptLine); }
+ { plat->clearPciInt(letoh(configData->config.interruptLine)); }
uint8_t
interruptLine()
- { return configData->config.interruptLine; }
+ { return letoh(configData->config.interruptLine); }
/** return the address ranges that this device responds to.
* @params range_list range list to populate with ranges
*/
void addressRanges(AddrRangeList &range_list);
+ /** Do a PCI Configspace memory access. */
+ Tick recvConfig(Packet *pkt)
+ { return pkt->isRead() ? readConfig(pkt) : writeConfig(pkt); }
+
/**
* Constructor for PCI Dev. This function copies data from the
* config file object PCIConfigData and registers the device with
@@ -193,30 +236,7 @@ class PciDev : public DmaDevice
*/
PciDev(Params *params);
- /**
- * Write to the PCI config space data that is stored locally. This may be
- * overridden by the device but at some point it will eventually call this
- * for normal operations that it does not need to override.
- * @param offset the offset into config space
- * @param size the size of the write
- * @param data the data to write
- */
- virtual void writeConfig(int offset, const uint8_t data);
- virtual void writeConfig(int offset, const uint16_t data);
- virtual void writeConfig(int offset, const uint32_t data);
-
-
- /**
- * Read from the PCI config space data that is stored locally. This may be
- * overridden by the device but at some point it will eventually call this
- * for normal operations that it does not need to override.
- * @param offset the offset into config space
- * @param size the size of the read
- * @param data pointer to the location where the read value should be stored
- */
- virtual void readConfig(int offset, uint8_t *data);
- virtual void readConfig(int offset, uint16_t *data);
- virtual void readConfig(int offset, uint32_t *data);
+ virtual void init();
/**
* Serialize this object to the given output stream.
@@ -230,5 +250,22 @@ class PciDev : public DmaDevice
* @param section The section name of this object
*/
virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+
+ virtual unsigned int drain(Event *de);
+
+ virtual Port *getPort(const std::string &if_name, int idx = -1)
+ {
+ if (if_name == "config") {
+ if (configPort != NULL)
+ panic("pciconfig port already connected to.");
+ configPort = new PciConfigPort(this, params()->busNum,
+ params()->deviceNum, params()->functionNum,
+ params()->platform);
+ return configPort;
+ }
+ return DmaDevice::getPort(if_name, idx);
+ }
+
};
#endif // __DEV_PCIDEV_HH__
diff --git a/src/dev/pcireg.h b/src/dev/pcireg.h
index 0aa4ba8ef..a48abd4fa 100644
--- a/src/dev/pcireg.h
+++ b/src/dev/pcireg.h
@@ -142,6 +142,7 @@ union PCIConfig {
// Device specific offsets
#define PCI_DEVICE_SPECIFIC 0x40 // 192 bytes
+#define PCI_CONFIG_SIZE 0xFF
// Some Vendor IDs
#define PCI_VENDOR_DEC 0x1011
diff --git a/src/dev/platform.cc b/src/dev/platform.cc
index ed021e3b6..8546b7805 100644
--- a/src/dev/platform.cc
+++ b/src/dev/platform.cc
@@ -63,5 +63,21 @@ Platform::pciToDma(Addr pciAddr) const
panic("No PCI dma support in platform.");
}
+void
+Platform::registerPciDevice(uint8_t bus, uint8_t dev, uint8_t func, uint8_t intr)
+{
+ uint32_t bdf = bus << 16 | dev << 8 | func << 0;
+ if (pciDevices.find(bdf) != pciDevices.end())
+ fatal("Two PCI devices have same bus:device:function\n");
+
+ if (intLines.test(intr))
+ fatal("Two PCI devices have same interrupt line: %d\n", intr);
+
+ pciDevices.insert(bdf);
+
+ intLines.set(intr);
+}
+
+
DEFINE_SIM_OBJECT_CLASS_NAME("Platform", Platform)
diff --git a/src/dev/platform.hh b/src/dev/platform.hh
index bfc229748..1940dcad6 100644
--- a/src/dev/platform.hh
+++ b/src/dev/platform.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Andrew Schultz
+ * Nathan Binkert
*/
/**
@@ -36,6 +37,9 @@
#ifndef __DEV_PLATFORM_HH__
#define __DEV_PLATFORM_HH__
+#include <bitset>
+#include <set>
+
#include "sim/sim_object.hh"
#include "arch/isa_traits.hh"
@@ -51,9 +55,6 @@ class Platform : public SimObject
/** Pointer to the interrupt controller */
IntrControl *intrctrl;
- /** Pointer to the PCI configuration space */
- PciConfigAll *pciconfig;
-
/** Pointer to the UART, set by the uart */
Uart *uart;
@@ -63,13 +64,20 @@ class Platform : public SimObject
public:
Platform(const std::string &name, IntrControl *intctrl);
virtual ~Platform();
- virtual void init() { if (pciconfig == NULL) panic("PCI Config not set"); }
virtual void postConsoleInt() = 0;
virtual void clearConsoleInt() = 0;
virtual Tick intrFrequency() = 0;
virtual void postPciInt(int line);
virtual void clearPciInt(int line);
virtual Addr pciToDma(Addr pciAddr) const;
+ virtual Addr calcConfigAddr(int bus, int dev, int func) = 0;
+ virtual void registerPciDevice(uint8_t bus, uint8_t dev, uint8_t func,
+ uint8_t intr);
+
+ private:
+ std::bitset<256> intLines;
+ std::set<uint32_t> pciDevices;
+
};
#endif // __DEV_PLATFORM_HH__
diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc
index a0223733b..815cecca5 100644
--- a/src/dev/sinic.cc
+++ b/src/dev/sinic.cc
@@ -37,7 +37,6 @@
#include "cpu/intr_control.hh"
#include "dev/etherlink.hh"
#include "dev/sinic.hh"
-#include "dev/pciconfigall.hh"
#include "mem/packet.hh"
#include "sim/builder.hh"
#include "sim/debug.hh"
@@ -922,7 +921,7 @@ Device::rxKick()
break;
case rxBeginCopy:
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
goto exit;
rxDmaAddr = params()->platform->pciToDma(
@@ -1110,7 +1109,7 @@ Device::txKick()
break;
case txBeginCopy:
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
goto exit;
txDmaAddr = params()->platform->pciToDma(
@@ -1288,6 +1287,18 @@ Device::recvPacket(EthPacketPtr packet)
return true;
}
+void
+Device::resume()
+{
+ SimObject::resume();
+
+ // During drain we could have left the state machines in a waiting state and
+ // they wouldn't get out until some other event occured to kick them.
+ // This way they'll get out immediately
+ txKick();
+ rxKick();
+}
+
//=====================================================================
//
//
@@ -1623,7 +1634,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
SimObjectParam<System *> system;
SimObjectParam<Platform *> platform;
- SimObjectParam<PciConfigAll *> configspace;
SimObjectParam<PciConfigData *> configdata;
Param<uint32_t> pci_bus;
Param<uint32_t> pci_dev;
@@ -1666,7 +1676,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM(system, "System pointer"),
INIT_PARAM(platform, "Platform pointer"),
- INIT_PARAM(configspace, "PCI Configspace"),
INIT_PARAM(configdata, "PCI Config data"),
INIT_PARAM(pci_bus, "PCI bus ID"),
INIT_PARAM(pci_dev, "PCI device number"),
@@ -1711,7 +1720,6 @@ CREATE_SIM_OBJECT(Device)
params->name = getInstanceName();
params->platform = platform;
params->system = system;
- params->configSpace = configspace;
params->configData = configdata;
params->busNum = pci_bus;
params->deviceNum = pci_dev;
diff --git a/src/dev/sinic.hh b/src/dev/sinic.hh
index f6c229039..eece4ba6b 100644
--- a/src/dev/sinic.hh
+++ b/src/dev/sinic.hh
@@ -266,6 +266,7 @@ class Device : public Base
public:
virtual Tick read(Packet *pkt);
virtual Tick write(Packet *pkt);
+ virtual void resume();
void prepareIO(int cpu, int index);
void prepareRead(int cpu, int index);
diff --git a/src/dev/tsunami.cc b/src/dev/tsunami.cc
index c9e15581d..8e740a72f 100644
--- a/src/dev/tsunami.cc
+++ b/src/dev/tsunami.cc
@@ -95,6 +95,13 @@ Tsunami::pciToDma(Addr pciAddr) const
return pchip->translatePciToDma(pciAddr);
}
+
+Addr
+Tsunami::calcConfigAddr(int bus, int dev, int func)
+{
+ return pchip->calcConfigAddr(bus, dev, func);
+}
+
void
Tsunami::serialize(std::ostream &os)
{
diff --git a/src/dev/tsunami.hh b/src/dev/tsunami.hh
index 13fc4417c..8bb66e914 100644
--- a/src/dev/tsunami.hh
+++ b/src/dev/tsunami.hh
@@ -113,9 +113,15 @@ class Tsunami : public Platform
*/
virtual void clearPciInt(int line);
+
virtual Addr pciToDma(Addr pciAddr) const;
/**
+ * Calculate the configuration address given a bus/dev/func.
+ */
+ virtual Addr calcConfigAddr(int bus, int dev, int func);
+
+ /**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
*/
diff --git a/src/dev/tsunami_pchip.cc b/src/dev/tsunami_pchip.cc
index a376b908d..8a542b9b0 100644
--- a/src/dev/tsunami_pchip.cc
+++ b/src/dev/tsunami_pchip.cc
@@ -302,6 +302,17 @@ TsunamiPChip::translatePciToDma(Addr busAddr)
// if no match was found, then return the original address
return busAddr;
}
+Addr
+TsunamiPChip::calcConfigAddr(int bus, int dev, int func)
+{
+ assert(func < 8);
+ assert(dev < 32);
+ assert(bus == 0);
+
+ return TsunamiPciBus0Config | (func << 8) | (dev << 11);
+}
+
+
void
TsunamiPChip::serialize(std::ostream &os)
diff --git a/src/dev/tsunami_pchip.hh b/src/dev/tsunami_pchip.hh
index 9f80f7d68..2c97a1fea 100644
--- a/src/dev/tsunami_pchip.hh
+++ b/src/dev/tsunami_pchip.hh
@@ -45,6 +45,9 @@
class TsunamiPChip : public BasicPioDevice
{
protected:
+
+ static const Addr TsunamiPciBus0Config = ULL(0x801fe000000);
+
/** Pchip control register */
uint64_t pctl;
@@ -80,6 +83,8 @@ class TsunamiPChip : public BasicPioDevice
*/
Addr translatePciToDma(Addr busAddr);
+ Addr calcConfigAddr(int bus, int dev, int func);
+
virtual Tick read(Packet *pkt);
virtual Tick write(Packet *pkt);
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-07 18:21:34 +0000