diff options
Diffstat (limited to 'src/dev')
-rw-r--r-- | src/dev/i8254xGBe.cc | 4 | ||||
-rw-r--r-- | src/dev/i8254xGBe.hh | 2 | ||||
-rw-r--r-- | src/dev/ns_gige.cc | 6 | ||||
-rw-r--r-- | src/dev/ns_gige.hh | 2 | ||||
-rw-r--r-- | src/dev/sinic.cc | 2 | ||||
-rw-r--r-- | src/dev/sinic.hh | 2 |
6 files changed, 9 insertions, 9 deletions
diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index 84882b056..460f6a9fb 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -1104,7 +1104,7 @@ IGbE::restartClock() { if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && getState() == SimObject::Running) - tickEvent.schedule((curTick/cycles(1)) * cycles(1) + cycles(1)); + tickEvent.schedule((curTick/ticks(1)) * ticks(1) + ticks(1)); } unsigned int @@ -1400,7 +1400,7 @@ IGbE::tick() if (rxTick || txTick || txFifoTick) - tickEvent.schedule(curTick + cycles(1)); + tickEvent.schedule(curTick + ticks(1)); } void diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh index cbe7cf8c0..30aa6430e 100644 --- a/src/dev/i8254xGBe.hh +++ b/src/dev/i8254xGBe.hh @@ -614,7 +614,7 @@ class IGbE : public EtherDevice virtual EtherInt *getEthPort(const std::string &if_name, int idx); Tick clock; - inline Tick cycles(int numCycles) const { return numCycles * clock; } + inline Tick ticks(int numCycles) const { return numCycles * clock; } virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index 0788b89a9..bd48bdca5 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -1469,7 +1469,7 @@ NSGigE::rxKick() } // Go to the next state machine clock tick. - rxKickTick = curTick + cycles(1); + rxKickTick = curTick + ticks(1); } switch(rxDmaState) { @@ -1916,7 +1916,7 @@ NSGigE::txKick() } // Go to the next state machine clock tick. - txKickTick = curTick + cycles(1); + txKickTick = curTick + ticks(1); } switch(txDmaState) { @@ -2322,7 +2322,7 @@ NSGigE::transferDone() DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n"); - txEvent.reschedule(curTick + cycles(1), true); + txEvent.reschedule(curTick + ticks(1), true); } bool diff --git a/src/dev/ns_gige.hh b/src/dev/ns_gige.hh index 5e589687a..dfdd81b66 100644 --- a/src/dev/ns_gige.hh +++ b/src/dev/ns_gige.hh @@ -199,7 +199,7 @@ class NSGigE : public EtherDevice /* state machine cycle time */ Tick clock; - inline Tick cycles(int numCycles) const { return numCycles * clock; } + inline Tick ticks(int numCycles) const { return numCycles * clock; } /* tx State Machine */ TxState txState; diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index 7457a2b47..c63966528 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -1211,7 +1211,7 @@ Device::transferDone() DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n"); - txEvent.reschedule(curTick + cycles(1), true); + txEvent.reschedule(curTick + ticks(1), true); } bool diff --git a/src/dev/sinic.hh b/src/dev/sinic.hh index 469b28191..e85d93fe4 100644 --- a/src/dev/sinic.hh +++ b/src/dev/sinic.hh @@ -51,7 +51,7 @@ class Base : public PciDev bool rxEnable; bool txEnable; Tick clock; - inline Tick cycles(int numCycles) const { return numCycles * clock; } + inline Tick ticks(int numCycles) const { return numCycles * clock; } protected: Tick intrDelay; |