diff options
Diffstat (limited to 'src/dev')
33 files changed, 74 insertions, 0 deletions
diff --git a/src/dev/BadDevice.py b/src/dev/BadDevice.py index 4fc592184..d6d68f86d 100644 --- a/src/dev/BadDevice.py +++ b/src/dev/BadDevice.py @@ -31,4 +31,5 @@ from Device import BasicPioDevice class BadDevice(BasicPioDevice): type = 'BadDevice' + cxx_header = "dev/baddev.hh" devicename = Param.String("Name of device to error on") diff --git a/src/dev/CopyEngine.py b/src/dev/CopyEngine.py index 9aa0e1fe5..68332e0a0 100644 --- a/src/dev/CopyEngine.py +++ b/src/dev/CopyEngine.py @@ -33,6 +33,7 @@ from Pci import PciDevice class CopyEngine(PciDevice): type = 'CopyEngine' + cxx_header = "dev/copy_engine.hh" dma = VectorMasterPort("Copy engine DMA port") VendorID = 0x8086 DeviceID = 0x1a38 diff --git a/src/dev/Device.py b/src/dev/Device.py index 3a06444cb..3b86ffb7d 100644 --- a/src/dev/Device.py +++ b/src/dev/Device.py @@ -32,24 +32,28 @@ from MemObject import MemObject class PioDevice(MemObject): type = 'PioDevice' + cxx_header = "dev/io_device.hh" abstract = True pio = SlavePort("Programmed I/O port") system = Param.System(Parent.any, "System this device is part of") class BasicPioDevice(PioDevice): type = 'BasicPioDevice' + cxx_header = "dev/io_device.hh" abstract = True pio_addr = Param.Addr("Device Address") pio_latency = Param.Latency('100ns', "Programmed IO latency") class DmaDevice(PioDevice): type = 'DmaDevice' + cxx_header = "dev/io_device.hh" abstract = True dma = MasterPort("DMA port") class IsaFake(BasicPioDevice): type = 'IsaFake' + cxx_header = "dev/io_device.hh" pio_size = Param.Addr(0x8, "Size of address range") ret_data8 = Param.UInt8(0xFF, "Default data to return") ret_data16 = Param.UInt16(0xFFFF, "Default data to return") diff --git a/src/dev/DiskImage.py b/src/dev/DiskImage.py index 92eb0553c..38cc6e75d 100644 --- a/src/dev/DiskImage.py +++ b/src/dev/DiskImage.py @@ -31,14 +31,17 @@ from m5.params import * class DiskImage(SimObject): type = 'DiskImage' abstract = True + cxx_header = "dev/disk_image.hh" image_file = Param.String("disk image file") read_only = Param.Bool(False, "read only image") class RawDiskImage(DiskImage): type = 'RawDiskImage' + cxx_header = "dev/disk_image.hh" class CowDiskImage(DiskImage): type = 'CowDiskImage' + cxx_header = "dev/disk_image.hh" child = Param.DiskImage(RawDiskImage(read_only=True), "child image") table_size = Param.Int(65536, "initial table size") diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py index 1afbce8ee..57d867fbe 100644 --- a/src/dev/Ethernet.py +++ b/src/dev/Ethernet.py @@ -34,9 +34,11 @@ from Pci import PciDevice class EtherObject(SimObject): type = 'EtherObject' abstract = True + cxx_header = "dev/etherobject.hh" class EtherLink(EtherObject): type = 'EtherLink' + cxx_header = "dev/etherlink.hh" int0 = SlavePort("interface 0") int1 = SlavePort("interface 1") delay = Param.Latency('0us', "packet transmit delay") @@ -46,29 +48,34 @@ class EtherLink(EtherObject): class EtherBus(EtherObject): type = 'EtherBus' + cxx_header = "dev/etherbus.hh" loopback = Param.Bool(True, "send packet back to the sending interface") dump = Param.EtherDump(NULL, "dump object") speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") class EtherTap(EtherObject): type = 'EtherTap' + cxx_header = "dev/ethertap.hh" bufsz = Param.Int(10000, "tap buffer size") dump = Param.EtherDump(NULL, "dump object") port = Param.UInt16(3500, "tap port") class EtherDump(SimObject): type = 'EtherDump' + cxx_header = "dev/etherdump.hh" file = Param.String("dump file") maxlen = Param.Int(96, "max portion of packet data to dump") class EtherDevice(PciDevice): type = 'EtherDevice' abstract = True + cxx_header = "dev/etherdevice.hh" interface = MasterPort("Ethernet Interface") class IGbE(EtherDevice): # Base class for two IGbE adapters listed above type = 'IGbE' + cxx_header = "dev/i8254xGBe.hh" hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") use_flow_control = Param.Bool(False, @@ -149,6 +156,7 @@ class EtherDevBase(EtherDevice): class NSGigE(EtherDevBase): type = 'NSGigE' + cxx_header = "dev/ns_gige.hh" dma_data_free = Param.Bool(False, "DMA of Data is free") dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") @@ -178,6 +186,7 @@ class NSGigE(EtherDevBase): class Sinic(EtherDevBase): type = 'Sinic' cxx_class = 'Sinic::Device' + cxx_header = "dev/sinic.hh" rx_max_copy = Param.MemorySize('1514B', "rx max copy") tx_max_copy = Param.MemorySize('16kB', "tx max copy") diff --git a/src/dev/Ide.py b/src/dev/Ide.py index 7d97c42b6..c5eef9f54 100644 --- a/src/dev/Ide.py +++ b/src/dev/Ide.py @@ -34,12 +34,14 @@ class IdeID(Enum): vals = ['master', 'slave'] class IdeDisk(SimObject): type = 'IdeDisk' + cxx_header = "dev/ide_disk.hh" delay = Param.Latency('1us', "Fixed disk delay in microseconds") driveID = Param.IdeID('master', "Drive ID") image = Param.DiskImage("Disk image") class IdeController(PciDevice): type = 'IdeController' + cxx_header = "dev/ide_ctrl.hh" disks = VectorParam.IdeDisk("IDE disks attached to this controller") VendorID = 0x8086 diff --git a/src/dev/Pci.py b/src/dev/Pci.py index 8b4fd7b2f..df7c773c4 100644 --- a/src/dev/Pci.py +++ b/src/dev/Pci.py @@ -33,6 +33,7 @@ from Device import BasicPioDevice, DmaDevice, PioDevice class PciConfigAll(PioDevice): type = 'PciConfigAll' + cxx_header = "dev/pciconfigall.hh" platform = Param.Platform(Parent.any, "Platform this device is part of.") pio_latency = Param.Latency('30ns', "Programmed IO latency") bus = Param.UInt8(0x00, "PCI bus to act as config space for") @@ -42,6 +43,7 @@ class PciConfigAll(PioDevice): class PciDevice(DmaDevice): type = 'PciDevice' cxx_class = 'PciDev' + cxx_header = "dev/pcidev.hh" abstract = True platform = Param.Platform(Parent.any, "Platform this device is part of.") config = SlavePort("PCI configuration space port") diff --git a/src/dev/Platform.py b/src/dev/Platform.py index cb414121b..8a9871b35 100644 --- a/src/dev/Platform.py +++ b/src/dev/Platform.py @@ -32,4 +32,5 @@ from m5.proxy import * class Platform(SimObject): type = 'Platform' abstract = True + cxx_header = "dev/platform.hh" intrctrl = Param.IntrControl(Parent.any, "interrupt controller") diff --git a/src/dev/SimpleDisk.py b/src/dev/SimpleDisk.py index cf28c9c19..88bf5dbfb 100644 --- a/src/dev/SimpleDisk.py +++ b/src/dev/SimpleDisk.py @@ -31,5 +31,6 @@ from m5.params import * from m5.proxy import * class SimpleDisk(SimObject): type = 'SimpleDisk' + cxx_header = "dev/simple_disk.hh" disk = Param.DiskImage("Disk Image") system = Param.System(Parent.any, "System Pointer") diff --git a/src/dev/Terminal.py b/src/dev/Terminal.py index d67019198..2b54f9d5e 100644 --- a/src/dev/Terminal.py +++ b/src/dev/Terminal.py @@ -32,6 +32,7 @@ from m5.proxy import * class Terminal(SimObject): type = 'Terminal' + cxx_header = "dev/terminal.hh" intr_control = Param.IntrControl(Parent.any, "interrupt controller") port = Param.TcpPort(3456, "listen port") number = Param.Int(0, "terminal number") diff --git a/src/dev/Uart.py b/src/dev/Uart.py index 3dfc885eb..c3bc9dd0f 100644 --- a/src/dev/Uart.py +++ b/src/dev/Uart.py @@ -33,8 +33,10 @@ from Device import BasicPioDevice class Uart(BasicPioDevice): type = 'Uart' abstract = True + cxx_header = "dev/uart.hh" platform = Param.Platform(Parent.any, "Platform this device is part of.") terminal = Param.Terminal(Parent.any, "The terminal") class Uart8250(Uart): type = 'Uart8250' + cxx_header = "dev/uart8250.hh" diff --git a/src/dev/alpha/AlphaBackdoor.py b/src/dev/alpha/AlphaBackdoor.py index 14894b863..29372bce8 100644 --- a/src/dev/alpha/AlphaBackdoor.py +++ b/src/dev/alpha/AlphaBackdoor.py @@ -33,6 +33,7 @@ from Device import BasicPioDevice class AlphaBackdoor(BasicPioDevice): type = 'AlphaBackdoor' + cxx_header = "dev/alpha/backdoor.hh" cpu = Param.BaseCPU(Parent.cpu[0], "Processor") disk = Param.SimpleDisk("Simple Disk") terminal = Param.Terminal(Parent.any, "The console terminal") diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py index 9a3ec0593..1a29b25d9 100644 --- a/src/dev/alpha/Tsunami.py +++ b/src/dev/alpha/Tsunami.py @@ -37,10 +37,12 @@ from Uart import Uart8250 class TsunamiCChip(BasicPioDevice): type = 'TsunamiCChip' + cxx_header = "dev/alpha/tsunami_cchip.hh" tsunami = Param.Tsunami(Parent.any, "Tsunami") class TsunamiIO(BasicPioDevice): type = 'TsunamiIO' + cxx_header = "dev/alpha/tsunami_io.hh" time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") year_is_bcd = Param.Bool(False, @@ -50,10 +52,12 @@ class TsunamiIO(BasicPioDevice): class TsunamiPChip(BasicPioDevice): type = 'TsunamiPChip' + cxx_header = "dev/alpha/tsunami_pchip.hh" tsunami = Param.Tsunami(Parent.any, "Tsunami") class Tsunami(Platform): type = 'Tsunami' + cxx_header = "dev/alpha/tsunami.hh" system = Param.System(Parent.any, "system") cchip = TsunamiCChip(pio_addr=0x801a0000000) diff --git a/src/dev/alpha/tsunami_io.hh b/src/dev/alpha/tsunami_io.hh index 212e2a3d5..7477fb124 100644 --- a/src/dev/alpha/tsunami_io.hh +++ b/src/dev/alpha/tsunami_io.hh @@ -38,6 +38,7 @@ #define __DEV_TSUNAMI_IO_HH__ #include "dev/alpha/tsunami.hh" +#include "dev/alpha/tsunami_cchip.hh" #include "dev/intel_8254_timer.hh" #include "dev/io_device.hh" #include "dev/mc146818.hh" diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index f0b629b38..87d4d9b16 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -54,11 +54,13 @@ from SimpleMemory import SimpleMemory class AmbaDevice(BasicPioDevice): type = 'AmbaDevice' abstract = True + cxx_header = "dev/arm/amba_device.hh" amba_id = Param.UInt32("ID of AMBA device for kernel detection") class AmbaIntDevice(AmbaDevice): type = 'AmbaIntDevice' abstract = True + cxx_header = "dev/arm/amba_device.hh" gic = Param.Gic(Parent.any, "Gic to use for interrupting") int_num = Param.UInt32("Interrupt number that connects to GIC") int_delay = Param.Latency("100ns", @@ -67,6 +69,7 @@ class AmbaIntDevice(AmbaDevice): class AmbaDmaDevice(DmaDevice): type = 'AmbaDmaDevice' abstract = True + cxx_header = "dev/arm/amba_device.hh" pio_addr = Param.Addr("Address for AMBA slave interface") pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") gic = Param.Gic(Parent.any, "Gic to use for interrupting") @@ -75,15 +78,18 @@ class AmbaDmaDevice(DmaDevice): class A9SCU(BasicPioDevice): type = 'A9SCU' + cxx_header = "dev/arm/a9scu.hh" class RealViewCtrl(BasicPioDevice): type = 'RealViewCtrl' + cxx_header = "dev/arm/rv_ctrl.hh" proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") class Gic(PioDevice): type = 'Gic' + cxx_header = "dev/arm/gic.hh" platform = Param.Platform(Parent.any, "Platform this device is part of.") dist_addr = Param.Addr(0x1f001000, "Address for distributor") cpu_addr = Param.Addr(0x1f000100, "Address for cpu") @@ -94,11 +100,13 @@ class Gic(PioDevice): class AmbaFake(AmbaDevice): type = 'AmbaFake' + cxx_header = "dev/arm/amba_fake.hh" ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") amba_id = 0; class Pl011(Uart): type = 'Pl011' + cxx_header = "dev/arm/pl011.hh" gic = Param.Gic(Parent.any, "Gic to use for interrupting") int_num = Param.UInt32("Interrupt number that connects to GIC") end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") @@ -106,6 +114,7 @@ class Pl011(Uart): class Sp804(AmbaDevice): type = 'Sp804' + cxx_header = "dev/arm/timer_sp804.hh" gic = Param.Gic(Parent.any, "Gic to use for interrupting") int_num0 = Param.UInt32("Interrupt number that connects to GIC") clock0 = Param.Clock('1MHz', "Clock speed of the input") @@ -115,6 +124,7 @@ class Sp804(AmbaDevice): class CpuLocalTimer(BasicPioDevice): type = 'CpuLocalTimer' + cxx_header = "dev/arm/timer_cpulocal.hh" gic = Param.Gic(Parent.any, "Gic to use for interrupting") int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") @@ -123,11 +133,13 @@ class CpuLocalTimer(BasicPioDevice): class PL031(AmbaIntDevice): type = 'PL031' + cxx_header = "dev/arm/rtc_pl031.hh" time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") amba_id = 0x00341031 class Pl050(AmbaIntDevice): type = 'Pl050' + cxx_header = "dev/arm/kmi.hh" vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") int_delay = '1us' @@ -135,6 +147,7 @@ class Pl050(AmbaIntDevice): class Pl111(AmbaDmaDevice): type = 'Pl111' + cxx_header = "dev/arm/pl111.hh" # Override the default clock clock = '24MHz' vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") @@ -142,6 +155,7 @@ class Pl111(AmbaDmaDevice): class RealView(Platform): type = 'RealView' + cxx_header = "dev/arm/realview.hh" system = Param.System(Parent.any, "system") pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") mem_start_addr = Param.Addr(0, "Start address of main memory") diff --git a/src/dev/arm/pl011.hh b/src/dev/arm/pl011.hh index dbd8bd539..e96d33d83 100644 --- a/src/dev/arm/pl011.hh +++ b/src/dev/arm/pl011.hh @@ -48,6 +48,8 @@ #ifndef __DEV_ARM_PL011_H__ #define __DEV_ARM_PL011_H__ +#include "base/bitfield.hh" +#include "base/bitunion.hh" #include "dev/io_device.hh" #include "dev/uart.hh" #include "params/Pl011.hh" diff --git a/src/dev/arm/realview.hh b/src/dev/arm/realview.hh index 70647d47c..f38aa69fc 100644 --- a/src/dev/arm/realview.hh +++ b/src/dev/arm/realview.hh @@ -52,6 +52,7 @@ #include "dev/platform.hh" #include "params/RealView.hh" +class Gic; class IdeController; class System; diff --git a/src/dev/arm/timer_cpulocal.hh b/src/dev/arm/timer_cpulocal.hh index cf7e46496..9b60db4ec 100644 --- a/src/dev/arm/timer_cpulocal.hh +++ b/src/dev/arm/timer_cpulocal.hh @@ -41,6 +41,7 @@ #ifndef __DEV_ARM_LOCALTIMER_HH__ #define __DEV_ARM_LOCALTIMER_HH__ +#include "base/bitunion.hh" #include "dev/io_device.hh" #include "params/CpuLocalTimer.hh" diff --git a/src/dev/copy_engine.hh b/src/dev/copy_engine.hh index 41b4a631e..9a0cb0628 100644 --- a/src/dev/copy_engine.hh +++ b/src/dev/copy_engine.hh @@ -50,6 +50,7 @@ #include <vector> +#include "base/cp_annotate.hh" #include "base/statistics.hh" #include "dev/copy_engine_defs.hh" #include "dev/pcidev.hh" diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py index 23a5e5c8f..290dabf01 100755 --- a/src/dev/mips/Malta.py +++ b/src/dev/mips/Malta.py @@ -37,10 +37,12 @@ from Uart import Uart8250 class MaltaCChip(BasicPioDevice): type = 'MaltaCChip' + cxx_header = "dev/mips/malta_cchip.hh" malta = Param.Malta(Parent.any, "Malta") class MaltaIO(BasicPioDevice): type = 'MaltaIO' + cxx_header = "dev/mips/malta_io.hh" time = Param.Time('01/01/2009', "System time to use (0 for actual time, default is 1/1/06)") year_is_bcd = Param.Bool(False, @@ -50,10 +52,12 @@ class MaltaIO(BasicPioDevice): class MaltaPChip(BasicPioDevice): type = 'MaltaPChip' + cxx_header = "dev/mips/malta_pchip.hh" malta = Param.Malta(Parent.any, "Malta") class Malta(Platform): type = 'Malta' + cxx_header = "dev/mips/malta.hh" system = Param.System(Parent.any, "system") cchip = MaltaCChip(pio_addr=0x801a0000000) io = MaltaIO(pio_addr=0x801fc000000) diff --git a/src/dev/mips/malta_io.hh b/src/dev/mips/malta_io.hh index 9311d7c22..9f49f20cc 100755 --- a/src/dev/mips/malta_io.hh +++ b/src/dev/mips/malta_io.hh @@ -38,6 +38,7 @@ #define __DEV_MALTA_IO_HH__ #include "dev/mips/malta.hh" +#include "dev/mips/malta_cchip.hh" #include "dev/intel_8254_timer.hh" #include "dev/io_device.hh" #include "dev/mc146818.hh" diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py index 03a59ac67..511f54b2c 100644 --- a/src/dev/sparc/T1000.py +++ b/src/dev/sparc/T1000.py @@ -36,22 +36,26 @@ from Uart import Uart8250 class MmDisk(BasicPioDevice): type = 'MmDisk' + cxx_header = "dev/sparc/mm_disk.hh" image = Param.DiskImage("Disk Image") pio_addr = 0x1F40000000 class DumbTOD(BasicPioDevice): type = 'DumbTOD' + cxx_header = "dev/sparc/dtod.hh" time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") pio_addr = 0xfff0c1fff8 class Iob(PioDevice): type = 'Iob' + cxx_header = "dev/sparc/iob.hh" platform = Param.Platform(Parent.any, "Platform this device is part of.") pio_latency = Param.Latency('1ns', "Programed IO latency") class T1000(Platform): type = 'T1000' + cxx_header = "dev/sparc/t1000.hh" system = Param.System(Parent.any, "system") fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) diff --git a/src/dev/x86/Cmos.py b/src/dev/x86/Cmos.py index 266fb8937..c0b2be58a 100644 --- a/src/dev/x86/Cmos.py +++ b/src/dev/x86/Cmos.py @@ -34,6 +34,7 @@ from X86IntPin import X86IntSourcePin class Cmos(BasicPioDevice): type = 'Cmos' cxx_class='X86ISA::Cmos' + cxx_header = "dev/x86/cmos.hh" time = Param.Time('01/01/2012', "System time to use ('Now' for actual time)") int_pin = Param.X86IntSourcePin(X86IntSourcePin(), diff --git a/src/dev/x86/I8042.py b/src/dev/x86/I8042.py index 57bf32ca0..d13a13341 100644 --- a/src/dev/x86/I8042.py +++ b/src/dev/x86/I8042.py @@ -34,6 +34,7 @@ from X86IntPin import X86IntSourcePin class I8042(BasicPioDevice): type = 'I8042' cxx_class = 'X86ISA::I8042' + cxx_header = "dev/x86/i8042.hh" # This isn't actually used for anything here. pio_addr = 0x0 data_port = Param.Addr('Data port address') diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py index 3b076a9d6..7e71cdfc1 100644 --- a/src/dev/x86/I82094AA.py +++ b/src/dev/x86/I82094AA.py @@ -34,6 +34,7 @@ from X86IntPin import X86IntSinkPin class I82094AA(BasicPioDevice): type = 'I82094AA' cxx_class = 'X86ISA::I82094AA' + cxx_header = "dev/x86/i82094aa.hh" apic_id = Param.Int(1, 'APIC id for this IO APIC') int_master = MasterPort("Port for sending interrupt messages") int_latency = Param.Latency('1ns', \ diff --git a/src/dev/x86/I8237.py b/src/dev/x86/I8237.py index 0121c3d24..a4c5e3ad5 100644 --- a/src/dev/x86/I8237.py +++ b/src/dev/x86/I8237.py @@ -33,3 +33,4 @@ from Device import BasicPioDevice class I8237(BasicPioDevice): type = 'I8237' cxx_class = 'X86ISA::I8237' + cxx_header = "dev/x86/i8237.hh" diff --git a/src/dev/x86/I8254.py b/src/dev/x86/I8254.py index 6fdcb1c8d..574dd81c2 100644 --- a/src/dev/x86/I8254.py +++ b/src/dev/x86/I8254.py @@ -34,5 +34,6 @@ from X86IntPin import X86IntSourcePin class I8254(BasicPioDevice): type = 'I8254' cxx_class = 'X86ISA::I8254' + cxx_header = "dev/x86/i8254.hh" int_pin = Param.X86IntSourcePin(X86IntSourcePin(), 'Pin to signal timer interrupts to') diff --git a/src/dev/x86/I8259.py b/src/dev/x86/I8259.py index 30ea14225..4403c3f53 100644 --- a/src/dev/x86/I8259.py +++ b/src/dev/x86/I8259.py @@ -40,6 +40,7 @@ class X86I8259CascadeMode(Enum): class I8259(BasicPioDevice): type = 'I8259' cxx_class='X86ISA::I8259' + cxx_header = "dev/x86/i8259.hh" output = Param.X86IntSourcePin(X86IntSourcePin(), 'The pin this I8259 drives') mode = Param.X86I8259CascadeMode('How this I8259 is cascaded') diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py index 91292788c..3fc2382b7 100644 --- a/src/dev/x86/Pc.py +++ b/src/dev/x86/Pc.py @@ -42,6 +42,7 @@ def x86IOAddress(port): class Pc(Platform): type = 'Pc' + cxx_header = "dev/x86/pc.hh" system = Param.System(Parent.any, "system") pciconfig = PciConfigAll() diff --git a/src/dev/x86/PcSpeaker.py b/src/dev/x86/PcSpeaker.py index cc1f5517a..f1c23157b 100644 --- a/src/dev/x86/PcSpeaker.py +++ b/src/dev/x86/PcSpeaker.py @@ -33,4 +33,5 @@ from Device import BasicPioDevice class PcSpeaker(BasicPioDevice): type = 'PcSpeaker' cxx_class = 'X86ISA::Speaker' + cxx_header = "dev/x86/speaker.hh" i8254 = Param.I8254('Timer that drives the speaker') diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index 7ac208d5e..45c49ce3a 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -45,6 +45,7 @@ def x86IOAddress(port): class SouthBridge(SimObject): type = 'SouthBridge' + cxx_header = "dev/x86/south_bridge.hh" platform = Param.Platform(Parent.any, "Platform this device is part of") _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master') diff --git a/src/dev/x86/X86IntPin.py b/src/dev/x86/X86IntPin.py index 35e274624..53760b496 100644 --- a/src/dev/x86/X86IntPin.py +++ b/src/dev/x86/X86IntPin.py @@ -33,11 +33,13 @@ from m5.SimObject import SimObject class X86IntSourcePin(SimObject): type = 'X86IntSourcePin' cxx_class = 'X86ISA::IntSourcePin' + cxx_header = "dev/x86/intdev.hh" # A generic pin to receive an interrupt signal generated by another device. class X86IntSinkPin(SimObject): type = 'X86IntSinkPin' cxx_class = 'X86ISA::IntSinkPin' + cxx_header = "dev/x86/intdev.hh" device = Param.SimObject("Device this pin belongs to") number = Param.Int("The pin number on the device") @@ -46,6 +48,7 @@ class X86IntSinkPin(SimObject): class X86IntLine(SimObject): type = 'X86IntLine' cxx_class = 'X86ISA::IntLine' + cxx_header = "dev/x86/intdev.hh" source = Param.X86IntSourcePin("Pin driving this line") sink = Param.X86IntSinkPin("Pin driven by this line") diff --git a/src/dev/x86/speaker.hh b/src/dev/x86/speaker.hh index 5aa1ccf0a..2886a76d7 100644 --- a/src/dev/x86/speaker.hh +++ b/src/dev/x86/speaker.hh @@ -32,6 +32,7 @@ #define __DEV_X86_SPEAKER_HH__ #include "base/bitunion.hh" +#include "dev/io_device.hh" #include "params/PcSpeaker.hh" namespace X86ISA |