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-rw-r--r--src/dev/x86/Pc.py2
-rw-r--r--src/dev/x86/SouthBridge.py17
2 files changed, 18 insertions, 1 deletions
diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index 7211fa3f4..6f315cbcb 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -67,7 +67,7 @@ class Pc(Platform):
fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8)
# A device to catch accesses to the non-existant floppy controller.
- fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=4)
+ fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2)
def attachIO(self, bus):
self.south_bridge.attachIO(bus)
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index a3db83610..be9276145 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -34,6 +34,7 @@ from I82094AA import I82094AA
from I8237 import I8237
from I8254 import I8254
from I8259 import I8259
+from Ide import IdeController
from PcSpeaker import PcSpeaker
from X86IntPin import X86IntLine
from m5.SimObject import SimObject
@@ -72,6 +73,21 @@ class SouthBridge(SimObject):
def connectPins(self, source, sink):
self.int_lines.append(X86IntLine(source=source, sink=sink))
+ # IDE controller
+ ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0)
+ ide.BAR0 = 0x1f0
+ ide.BAR0LegacyIO = True
+ ide.BAR1 = 0x3f4
+ ide.BAR1Size = '3B'
+ ide.BAR1LegacyIO = True
+ ide.BAR2 = 0x170
+ ide.BAR2LegacyIO = True
+ ide.BAR3 = 0x374
+ ide.BAR3Size = '3B'
+ ide.BAR3LegacyIO = True
+ ide.BAR4 = 1
+ ide.Command = 1
+
def attachIO(self, bus):
# Route interupt signals
self.connectPins(self.pic1.output, self.io_apic.pin(0))
@@ -94,6 +110,7 @@ class SouthBridge(SimObject):
# Connect to the bus
self.cmos.pio = bus.port
self.dma1.pio = bus.port
+ self.ide.pio = bus.port
self.keyboard.pio = bus.port
self.pic1.pio = bus.port
self.pic2.pio = bus.port