diff options
Diffstat (limited to 'src/gpu-compute/tlb_coalescer.cc')
| -rw-r--r-- | src/gpu-compute/tlb_coalescer.cc | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/gpu-compute/tlb_coalescer.cc b/src/gpu-compute/tlb_coalescer.cc index 9c5d30b92..68d2689ef 100644 --- a/src/gpu-compute/tlb_coalescer.cc +++ b/src/gpu-compute/tlb_coalescer.cc @@ -38,6 +38,7 @@ #include <cstring> #include "debug/GPUTLB.hh" +#include "sim/process.hh" TLBCoalescer::TLBCoalescer(const Params *p) : MemObject(p), @@ -155,14 +156,13 @@ TLBCoalescer::updatePhysAddresses(PacketPtr pkt) TheISA::GpuTLB::TranslationState *sender_state = safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState); - TheISA::GpuTlbEntry *tlb_entry = sender_state->tlbEntry; + TheISA::TlbEntry *tlb_entry = sender_state->tlbEntry; assert(tlb_entry); Addr first_entry_vaddr = tlb_entry->vaddr; Addr first_entry_paddr = tlb_entry->paddr; int page_size = tlb_entry->size(); bool uncacheable = tlb_entry->uncacheable; int first_hit_level = sender_state->hitLevel; - bool valid = tlb_entry->valid; // Get the physical page address of the translated request // Using the page_size specified in the TLBEntry allows us @@ -197,9 +197,10 @@ TLBCoalescer::updatePhysAddresses(PacketPtr pkt) // update senderState->tlbEntry, so we can insert // the correct TLBEentry in the TLBs above. + auto p = sender_state->tc->getProcessPtr(); sender_state->tlbEntry = - new TheISA::GpuTlbEntry(0, first_entry_vaddr, first_entry_paddr, - valid); + new TheISA::TlbEntry(p->pid(), first_entry_vaddr, + first_entry_paddr, false, false); // update the hitLevel for all uncoalesced reqs // so that each packet knows where it hit |