4 files changed, 16 insertions, 14 deletions

diff --git a/src/gpu-compute/gpu_dyn_inst.hh b/src/gpu-compute/gpu_dyn_inst.hh
index 0d357de38..9e63c4459 100644
--- a/src/gpu-compute/gpu_dyn_inst.hh
+++ b/src/gpu-compute/gpu_dyn_inst.hh
@@ -39,6 +39,7 @@
 #include <cstdint>
 #include <string>
 
+#include "base/logging.hh"
 #include "enums/MemType.hh"
 #include "enums/StorageClassType.hh"
 #include "gpu-compute/compute_unit.hh"
@@ -407,8 +408,7 @@ class GPUDynInst : public GPUExecContext
         } else if (isGroupSeg()) {
             req->setMemSpaceConfigFlags(Request::GROUP_SEGMENT);
         } else if (isFlat()) {
-            // TODO: translate to correct scope
-            assert(false);
+            panic("TODO: translate to correct scope");
         } else {
             fatal("%s has bad segment type\n", disassemble());
         }
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index fea6183ed..dbf7d2628 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -45,6 +45,7 @@
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/x86_traits.hh"
 #include "base/bitfield.hh"
+#include "base/logging.hh"
 #include "base/output.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
@@ -1150,16 +1151,16 @@ namespace X86ISA
 
         if ((inUser && !tlb_entry->user) ||
             (mode == BaseTLB::Write && badWrite)) {
-           // The page must have been present to get into the TLB in
-           // the first place. We'll assume the reserved bits are
-           // fine even though we're not checking them.
-           assert(false);
+            // The page must have been present to get into the TLB in
+            // the first place. We'll assume the reserved bits are
+            // fine even though we're not checking them.
+            panic("Page fault detected");
         }
 
         if (storeCheck && badWrite) {
-           // This would fault if this were a write, so return a page
-           // fault that reflects that happening.
-           assert(false);
+            // This would fault if this were a write, so return a page
+            // fault that reflects that happening.
+            panic("Page fault detected");
         }
     }
 
@@ -1362,7 +1363,7 @@ namespace X86ISA
              */
             handleTranslationReturn(virtPageAddr, TLB_MISS, pkt);
         } else {
-            assert(false);
+            panic("Unexpected TLB outcome %d", outcome);
         }
     }
 
@@ -1607,7 +1608,7 @@ namespace X86ISA
     {
         // The CPUSidePort never sends anything but replies. No retries
         // expected.
-        assert(false);
+        panic("recvReqRetry called");
     }
 
     AddrRangeList
@@ -1648,7 +1649,7 @@ namespace X86ISA
     {
         // No retries should reach the TLB. The retries
         // should only reach the TLBCoalescer.
-        assert(false);
+        panic("recvReqRetry called");
     }
 
     void
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 04d9bfce8..9ca478d91 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -272,7 +272,7 @@ namespace X86ISA
             virtual void recvFunctional(PacketPtr pkt);
             virtual void recvRangeChange() { }
             virtual void recvReqRetry();
-            virtual void recvRespRetry() { assert(false); }
+            virtual void recvRespRetry() { panic("recvRespRetry called"); }
             virtual AddrRangeList getAddrRanges() const;
         };
 
diff --git a/src/gpu-compute/tlb_coalescer.cc b/src/gpu-compute/tlb_coalescer.cc
index 68d2689ef..193c44ed8 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -37,6 +37,7 @@
 
 #include <cstring>
 
+#include "base/logging.hh"
 #include "debug/GPUTLB.hh"
 #include "sim/process.hh"
 
@@ -335,7 +336,7 @@ TLBCoalescer::CpuSidePort::recvTimingReq(PacketPtr pkt)
 void
 TLBCoalescer::CpuSidePort::recvReqRetry()
 {
-    assert(false);
+    panic("recvReqRetry called");
 }
 
 void