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-rw-r--r--src/gpu-compute/GPU.py3
-rw-r--r--src/gpu-compute/LdsState.py4
-rw-r--r--src/gpu-compute/X86GPUTLB.py9
-rw-r--r--src/gpu-compute/compute_unit.cc4
-rw-r--r--src/gpu-compute/compute_unit.hh4
-rw-r--r--src/gpu-compute/gpu_tlb.cc4
-rw-r--r--src/gpu-compute/gpu_tlb.hh4
-rw-r--r--src/gpu-compute/lds_state.cc2
-rw-r--r--src/gpu-compute/lds_state.hh4
-rw-r--r--src/gpu-compute/tlb_coalescer.cc4
-rw-r--r--src/gpu-compute/tlb_coalescer.hh6
11 files changed, 24 insertions, 24 deletions
diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py
index 9eb662abc..fee025435 100644
--- a/src/gpu-compute/GPU.py
+++ b/src/gpu-compute/GPU.py
@@ -40,7 +40,6 @@ from m5.SimObject import SimObject
from m5.objects.ClockedObject import ClockedObject
from m5.objects.Device import DmaDevice
-from m5.objects.MemObject import MemObject
from m5.objects.Process import EmulatedDriver
from m5.objects.Bridge import Bridge
from m5.objects.LdsState import LdsState
@@ -72,7 +71,7 @@ class Wavefront(SimObject):
wf_slot_id = Param.Int('wavefront id (0-ComputeUnit.max_wfs)')
wfSize = Param.Int(64, 'Wavefront size (in work items)')
-class ComputeUnit(MemObject):
+class ComputeUnit(ClockedObject):
type = 'ComputeUnit'
cxx_class = 'ComputeUnit'
cxx_header = 'gpu-compute/compute_unit.hh'
diff --git a/src/gpu-compute/LdsState.py b/src/gpu-compute/LdsState.py
index f1f8cd18a..a21bde06e 100644
--- a/src/gpu-compute/LdsState.py
+++ b/src/gpu-compute/LdsState.py
@@ -35,9 +35,9 @@ from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class LdsState(MemObject):
+class LdsState(ClockedObject):
type = 'LdsState'
cxx_class = 'LdsState'
cxx_header = 'gpu-compute/lds_state.hh'
diff --git a/src/gpu-compute/X86GPUTLB.py b/src/gpu-compute/X86GPUTLB.py
index 963e2d147..a0ac9e9e6 100644
--- a/src/gpu-compute/X86GPUTLB.py
+++ b/src/gpu-compute/X86GPUTLB.py
@@ -35,16 +35,17 @@ from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
+from m5.SimObject import SimObject
if buildEnv['FULL_SYSTEM']:
- class X86PagetableWalker(MemObject):
+ class X86PagetableWalker(SimObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
port = SlavePort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
-class X86GPUTLB(MemObject):
+class X86GPUTLB(ClockedObject):
type = 'X86GPUTLB'
cxx_class = 'X86ISA::GpuTLB'
cxx_header = 'gpu-compute/gpu_tlb.hh'
@@ -64,7 +65,7 @@ class X86GPUTLB(MemObject):
allocationPolicy = Param.Bool(True, "Allocate on an access")
accessDistance = Param.Bool(False, "print accessDistance stats")
-class TLBCoalescer(MemObject):
+class TLBCoalescer(ClockedObject):
type = 'TLBCoalescer'
cxx_class = 'TLBCoalescer'
cxx_header = 'gpu-compute/tlb_coalescer.hh'
diff --git a/src/gpu-compute/compute_unit.cc b/src/gpu-compute/compute_unit.cc
index fd328adca..a9571eed1 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -58,7 +58,7 @@
#include "mem/page_table.hh"
#include "sim/process.hh"
-ComputeUnit::ComputeUnit(const Params *p) : MemObject(p), fetchStage(p),
+ComputeUnit::ComputeUnit(const Params *p) : ClockedObject(p), fetchStage(p),
scoreboardCheckStage(p), scheduleStage(p), execStage(p),
globalMemoryPipe(p), localMemoryPipe(p), rrNextMemID(0), rrNextALUWp(0),
cu_id(p->cu_id), vrf(p->vector_register_file), numSIMDs(p->num_SIMDs),
@@ -1397,7 +1397,7 @@ ComputeUnit::ITLBPort::recvReqRetry()
void
ComputeUnit::regStats()
{
- MemObject::regStats();
+ ClockedObject::regStats();
vALUInsts
.name(name() + ".valu_insts")
diff --git a/src/gpu-compute/compute_unit.hh b/src/gpu-compute/compute_unit.hh
index cfe25d7d8..adf3c21d2 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -53,8 +53,8 @@
#include "gpu-compute/qstruct.hh"
#include "gpu-compute/schedule_stage.hh"
#include "gpu-compute/scoreboard_check_stage.hh"
-#include "mem/mem_object.hh"
#include "mem/port.hh"
+#include "sim/clocked_object.hh"
static const int MAX_REGS_FOR_NON_VEC_MEM_INST = 1;
static const int MAX_WIDTH_FOR_MEM_INST = 32;
@@ -91,7 +91,7 @@ enum TLB_CACHE
TLB_HIT_CACHE_HIT
};
-class ComputeUnit : public MemObject
+class ComputeUnit : public ClockedObject
{
public:
FetchStage fetchStage;
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index c23b9986f..ee405e872 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -61,7 +61,7 @@ namespace X86ISA
{
GpuTLB::GpuTLB(const Params *p)
- : MemObject(p), configAddress(0), size(p->size),
+ : ClockedObject(p), configAddress(0), size(p->size),
cleanupEvent([this]{ cleanup(); }, name(), false,
Event::Maximum_Pri),
exitEvent([this]{ exitCallback(); }, name())
@@ -950,7 +950,7 @@ namespace X86ISA
void
GpuTLB::regStats()
{
- MemObject::regStats();
+ ClockedObject::regStats();
localNumTLBAccesses
.name(name() + ".local_TLB_accesses")
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 80510d7a0..766d2d1b9 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -50,10 +50,10 @@
#include "base/logging.hh"
#include "base/statistics.hh"
#include "gpu-compute/compute_unit.hh"
-#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "mem/request.hh"
#include "params/X86GPUTLB.hh"
+#include "sim/clocked_object.hh"
#include "sim/sim_object.hh"
class BaseTLB;
@@ -62,7 +62,7 @@ class ThreadContext;
namespace X86ISA
{
- class GpuTLB : public MemObject
+ class GpuTLB : public ClockedObject
{
protected:
friend class Walker;
diff --git a/src/gpu-compute/lds_state.cc b/src/gpu-compute/lds_state.cc
index 48827c514..459a7a4cc 100644
--- a/src/gpu-compute/lds_state.cc
+++ b/src/gpu-compute/lds_state.cc
@@ -48,7 +48,7 @@
* the default constructor that works with SWIG
*/
LdsState::LdsState(const Params *params) :
- MemObject(params),
+ ClockedObject(params),
tickEvent(this),
cuPort(name() + ".port", this),
maximumSize(params->size),
diff --git a/src/gpu-compute/lds_state.hh b/src/gpu-compute/lds_state.hh
index 05bc11ed6..9b9cb1264 100644
--- a/src/gpu-compute/lds_state.hh
+++ b/src/gpu-compute/lds_state.hh
@@ -46,9 +46,9 @@
#include "enums/MemType.hh"
#include "gpu-compute/misc.hh"
-#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "params/LdsState.hh"
+#include "sim/clocked_object.hh"
class ComputeUnit;
@@ -108,7 +108,7 @@ class LdsChunk
// Local Data Share (LDS) State per Wavefront (contents of the LDS region
// allocated to the WorkGroup of this Wavefront)
-class LdsState: public MemObject
+class LdsState: public ClockedObject
{
protected:
diff --git a/src/gpu-compute/tlb_coalescer.cc b/src/gpu-compute/tlb_coalescer.cc
index 3b7631a74..999007c13 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -42,7 +42,7 @@
#include "sim/process.hh"
TLBCoalescer::TLBCoalescer(const Params *p)
- : MemObject(p),
+ : ClockedObject(p),
clock(p->clk_domain->clockPeriod()),
TLBProbesPerCycle(p->probesPerCycle),
coalescingWindow(p->coalescingWindow),
@@ -525,7 +525,7 @@ TLBCoalescer::processCleanupEvent()
void
TLBCoalescer::regStats()
{
- MemObject::regStats();
+ ClockedObject::regStats();
uncoalescedAccesses
.name(name() + ".uncoalesced_accesses")
diff --git a/src/gpu-compute/tlb_coalescer.hh b/src/gpu-compute/tlb_coalescer.hh
index 2aff81027..b65f1b0fb 100644
--- a/src/gpu-compute/tlb_coalescer.hh
+++ b/src/gpu-compute/tlb_coalescer.hh
@@ -49,23 +49,23 @@
#include "base/logging.hh"
#include "base/statistics.hh"
#include "gpu-compute/gpu_tlb.hh"
-#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "mem/request.hh"
#include "params/TLBCoalescer.hh"
+#include "sim/clocked_object.hh"
class BaseTLB;
class Packet;
class ThreadContext;
/**
- * The TLBCoalescer is a MemObject sitting on the front side (CPUSide) of
+ * The TLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of
* each TLB. It receives packets and issues coalesced requests to the
* TLB below it. It controls how requests are coalesced (the rules)
* and the permitted number of TLB probes per cycle (i.e., how many
* coalesced requests it feeds the TLB per cycle).
*/
-class TLBCoalescer : public MemObject
+class TLBCoalescer : public ClockedObject
{
protected:
// TLB clock: will inherit clock from shader's clock period in terms
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-25 23:48:56 +0000