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-rw-r--r--src/gpu-compute/compute_unit.hh4
-rw-r--r--src/gpu-compute/dispatcher.cc6
-rw-r--r--src/gpu-compute/dispatcher.hh4
-rw-r--r--src/gpu-compute/gpu_tlb.cc20
-rw-r--r--src/gpu-compute/gpu_tlb.hh7
-rw-r--r--src/gpu-compute/lds_state.hh4
-rw-r--r--src/gpu-compute/tlb_coalescer.cc20
-rw-r--r--src/gpu-compute/tlb_coalescer.hh4
8 files changed, 25 insertions, 44 deletions
diff --git a/src/gpu-compute/compute_unit.hh b/src/gpu-compute/compute_unit.hh
index c15e7e0f3..cfe25d7d8 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -691,8 +691,8 @@ class ComputeUnit : public MemObject
// port to the SQC TLB (there's a separate TLB for each I-cache)
ITLBPort *sqcTLBPort;
- virtual BaseMasterPort&
- getMasterPort(const std::string &if_name, PortID idx)
+ Port &
+ getPort(const std::string &if_name, PortID idx) override
{
if (if_name == "memory_port") {
memPort[idx] = new DataPort(csprintf("%s-port%d", name(), idx),
diff --git a/src/gpu-compute/dispatcher.cc b/src/gpu-compute/dispatcher.cc
index db250c28b..211e399d2 100644
--- a/src/gpu-compute/dispatcher.cc
+++ b/src/gpu-compute/dispatcher.cc
@@ -251,14 +251,14 @@ GpuDispatcher::write(PacketPtr pkt)
}
-BaseMasterPort&
-GpuDispatcher::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+GpuDispatcher::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "translation_port") {
return *tlbPort;
}
- return DmaDevice::getMasterPort(if_name, idx);
+ return DmaDevice::getPort(if_name, idx);
}
void
diff --git a/src/gpu-compute/dispatcher.hh b/src/gpu-compute/dispatcher.hh
index 92956e2d5..17dc5a5cc 100644
--- a/src/gpu-compute/dispatcher.hh
+++ b/src/gpu-compute/dispatcher.hh
@@ -140,8 +140,8 @@ class GpuDispatcher : public DmaDevice
TLBPort *tlbPort;
- virtual BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
AddrRangeList getAddrRanges() const;
Tick read(PacketPtr pkt);
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index 9e07b0547..c23b9986f 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -137,33 +137,25 @@ namespace X86ISA
assert(translationReturnEvent.empty());
}
- BaseSlavePort&
- GpuTLB::getSlavePort(const std::string &if_name, PortID idx)
+ Port &
+ GpuTLB::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "slave") {
if (idx >= static_cast<PortID>(cpuSidePort.size())) {
- panic("TLBCoalescer::getSlavePort: unknown index %d\n", idx);
+ panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
return *cpuSidePort[idx];
- } else {
- panic("TLBCoalescer::getSlavePort: unknown port %s\n", if_name);
- }
- }
-
- BaseMasterPort&
- GpuTLB::getMasterPort(const std::string &if_name, PortID idx)
- {
- if (if_name == "master") {
+ } else if (if_name == "master") {
if (idx >= static_cast<PortID>(memSidePort.size())) {
- panic("TLBCoalescer::getMasterPort: unknown index %d\n", idx);
+ panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
hasMemSidePort = true;
return *memSidePort[idx];
} else {
- panic("TLBCoalescer::getMasterPort: unknown port %s\n", if_name);
+ panic("TLBCoalescer::getPort: unknown port %s\n", if_name);
}
}
diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh
index 9ca478d91..80510d7a0 100644
--- a/src/gpu-compute/gpu_tlb.hh
+++ b/src/gpu-compute/gpu_tlb.hh
@@ -308,11 +308,8 @@ namespace X86ISA
// TLB ports on the memory side
std::vector<MemSidePort*> memSidePort;
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx=InvalidPortID);
-
- BaseSlavePort &getSlavePort(const std::string &if_name,
- PortID idx=InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/**
* TLB TranslationState: this currently is a somewhat bastardization of
diff --git a/src/gpu-compute/lds_state.hh b/src/gpu-compute/lds_state.hh
index ccf758b47..05bc11ed6 100644
--- a/src/gpu-compute/lds_state.hh
+++ b/src/gpu-compute/lds_state.hh
@@ -436,8 +436,8 @@ class LdsState: public MemObject
return range;
}
- virtual BaseSlavePort &
- getSlavePort(const std::string& if_name, PortID idx)
+ Port &
+ getPort(const std::string &if_name, PortID idx)
{
if (if_name == "cuPort") {
// TODO need to set name dynamically at this point?
diff --git a/src/gpu-compute/tlb_coalescer.cc b/src/gpu-compute/tlb_coalescer.cc
index 193c44ed8..3b7631a74 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -67,31 +67,23 @@ TLBCoalescer::TLBCoalescer(const Params *p)
}
}
-BaseSlavePort&
-TLBCoalescer::getSlavePort(const std::string &if_name, PortID idx)
+Port &
+TLBCoalescer::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "slave") {
if (idx >= static_cast<PortID>(cpuSidePort.size())) {
- panic("TLBCoalescer::getSlavePort: unknown index %d\n", idx);
+ panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
return *cpuSidePort[idx];
- } else {
- panic("TLBCoalescer::getSlavePort: unknown port %s\n", if_name);
- }
-}
-
-BaseMasterPort&
-TLBCoalescer::getMasterPort(const std::string &if_name, PortID idx)
-{
- if (if_name == "master") {
+ } else if (if_name == "master") {
if (idx >= static_cast<PortID>(memSidePort.size())) {
- panic("TLBCoalescer::getMasterPort: unknown index %d\n", idx);
+ panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
return *memSidePort[idx];
} else {
- panic("TLBCoalescer::getMasterPort: unknown port %s\n", if_name);
+ panic("TLBCoalescer::getPort: unknown port %s\n", if_name);
}
}
diff --git a/src/gpu-compute/tlb_coalescer.hh b/src/gpu-compute/tlb_coalescer.hh
index 0294e4ff4..2aff81027 100644
--- a/src/gpu-compute/tlb_coalescer.hh
+++ b/src/gpu-compute/tlb_coalescer.hh
@@ -211,8 +211,8 @@ class TLBCoalescer : public MemObject
// Coalescer master ports on the memory side
std::vector<MemSidePort*> memSidePort;
- BaseMasterPort& getMasterPort(const std::string &if_name, PortID idx);
- BaseSlavePort& getSlavePort(const std::string &if_name, PortID idx);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
void processProbeTLBEvent();
/// This event issues the TLB probes
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-09 22:30:23 +0000