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-rw-r--r--src/learning_gem5/part2/SimpleObject.py5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/learning_gem5/part2/SimpleObject.py b/src/learning_gem5/part2/SimpleObject.py
index ee7e9aef2..18ae60e3c 100644
--- a/src/learning_gem5/part2/SimpleObject.py
+++ b/src/learning_gem5/part2/SimpleObject.py
@@ -28,8 +28,13 @@
# Authors: Jason Lowe-Power
from m5.params import *
+# m5.proxy for Parent
+from m5.proxy import *
from m5.SimObject import SimObject
class SimpleObject(SimObject):
type = 'SimpleObject'
cxx_header = "learning_gem5/part2/simple_object.hh"
+ mem_side = MasterPort("memory side port, send requests")
+ isread = Param.Bool(True, "is it going to read memory")
+ system = Param.System(Parent.any, "system object")