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-rw-r--r--src/learning_gem5/part2/SimpleObject.py5
-rw-r--r--src/learning_gem5/part2/simple_object.cc53
-rw-r--r--src/learning_gem5/part2/simple_object.hh37
3 files changed, 94 insertions, 1 deletions
diff --git a/src/learning_gem5/part2/SimpleObject.py b/src/learning_gem5/part2/SimpleObject.py
index ee7e9aef2..18ae60e3c 100644
--- a/src/learning_gem5/part2/SimpleObject.py
+++ b/src/learning_gem5/part2/SimpleObject.py
@@ -28,8 +28,13 @@
# Authors: Jason Lowe-Power
from m5.params import *
+# m5.proxy for Parent
+from m5.proxy import *
from m5.SimObject import SimObject
class SimpleObject(SimObject):
type = 'SimpleObject'
cxx_header = "learning_gem5/part2/simple_object.hh"
+ mem_side = MasterPort("memory side port, send requests")
+ isread = Param.Bool(True, "is it going to read memory")
+ system = Param.System(Parent.any, "system object")
diff --git a/src/learning_gem5/part2/simple_object.cc b/src/learning_gem5/part2/simple_object.cc
index f340f1327..76dadf9c8 100644
--- a/src/learning_gem5/part2/simple_object.cc
+++ b/src/learning_gem5/part2/simple_object.cc
@@ -32,12 +32,63 @@
#include <iostream>
+#include "mem/packet.hh"
+#include "mem/request.hh"
+#include "sim/system.hh"
+
SimpleObject::SimpleObject(SimpleObjectParams *params) :
- SimObject(params)
+ SimObject(params),
+ masterId(params->system->getMasterId(this)),
+ memPort(params->name + ".mem_side", this),
+ isread(params->isread),
+ event([this] { processEvent(); }, name() + ".event")
{
std::cout << "Hello World! From a SimObject!" << std::endl;
}
+void SimpleObject::processEvent()
+{
+ readAtomic();
+}
+
+void SimpleObject::readAtomic()
+{
+ uint32_t val = 0;
+
+ RequestPtr req = std::make_shared<Request>(0x200000, 4, 0, masterId);
+ PacketPtr pkt = Packet::createRead(req);
+
+ pkt->dataStatic(&val);
+ // pkt->setData((const uint8_t *)&x);
+
+ Tick t = memPort.sendAtomic(pkt);
+ std::cout << "sendAtomic read " << t << " ticks." << std::endl;
+ std::cout << "read value 0x" << std::hex << val << std::endl;
+}
+
+void SimpleObject::writeAtomic()
+{
+ RequestPtr req = std::make_shared<Request>(0x200000, 4, 0, masterId);
+ PacketPtr pkt = Packet::createWrite(req);
+
+ uint32_t x = 0xdeadbeef;
+ pkt->dataStatic(&x);
+ // pkt->setData((const uint8_t *)&x);
+
+ Tick t = memPort.sendAtomic(pkt);
+ std::cout << "sendAtomic write " << t << " ticks." << std::endl;
+}
+
+void SimpleObject::startup()
+{
+ if (!isread) {
+ writeAtomic();
+ } else {
+ schedule(event, 40000);
+ }
+
+}
+
SimpleObject*
SimpleObjectParams::create()
{
diff --git a/src/learning_gem5/part2/simple_object.hh b/src/learning_gem5/part2/simple_object.hh
index 53a6ec919..53fa1fea1 100644
--- a/src/learning_gem5/part2/simple_object.hh
+++ b/src/learning_gem5/part2/simple_object.hh
@@ -31,13 +31,50 @@
#ifndef __LEARNING_GEM5_SIMPLE_OBJECT_HH__
#define __LEARNING_GEM5_SIMPLE_OBJECT_HH__
+#include "mem/port.hh"
#include "params/SimpleObject.hh"
#include "sim/sim_object.hh"
class SimpleObject : public SimObject
{
+ class SimplePort: public MasterPort
+ {
+ public:
+ // these virtual functions must be implemented
+ virtual bool recvTimingResp(PacketPtr pkt)
+ {
+ fatal("SimplePort::recvTimingResp not implemented!\n");
+ }
+ virtual void recvReqRetry()
+ {
+ fatal("SimplePort::recvReqRetry not implemented!\n");
+ }
+ // SimplePort::SimplePort() is deleted
+ SimplePort(const std::string &name, SimpleObject *owner):
+ MasterPort(name, owner)
+ {
+ }
+
+ };
+
+ MasterID masterId;
+ SimplePort memPort;
+ bool isread;
+ EventFunctionWrapper event;
+
public:
SimpleObject(SimpleObjectParams *p);
+ virtual Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override
+ {
+ if (if_name == "mem_side")
+ return memPort;
+ return SimpleObject::getPort(if_name, idx);
+ }
+ virtual void startup() override;
+ void processEvent();
+ void readAtomic();
+ void writeAtomic();
};
#endif // __LEARNING_GEM5_SIMPLE_OBJECT_HH__