diff options
Diffstat (limited to 'src/mem/Bridge.py')
| -rw-r--r-- | src/mem/Bridge.py | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py index ea8684e1b..62dfb7351 100644 --- a/src/mem/Bridge.py +++ b/src/mem/Bridge.py @@ -1,3 +1,15 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # @@ -25,6 +37,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Ali Saidi +# Andreas Hansson from m5.params import * from MemObject import MemObject @@ -34,9 +47,7 @@ class Bridge(MemObject): slave = SlavePort('Slave port') master = MasterPort('Master port') req_size = Param.Int(16, "The number of requests to buffer") - resp_size = Param.Int(16, "The number of requests to buffer") + resp_size = Param.Int(16, "The number of responses to buffer") delay = Param.Latency('0ns', "The latency of this bridge") - nack_delay = Param.Latency('0ns', "The latency of this bridge") - write_ack = Param.Bool(False, "Should this bridge ack writes") ranges = VectorParam.AddrRange([AllMemory], "Address ranges to pass through the bridge") |