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-rw-r--r--src/mem/Bridge.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 62dfb7351..5f2cc9f40 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -44,6 +44,7 @@ from MemObject import MemObject
class Bridge(MemObject):
type = 'Bridge'
+ cxx_header = "mem/bridge.hh"
slave = SlavePort('Slave port')
master = MasterPort('Master port')
req_size = Param.Int(16, "The number of requests to buffer")