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Diffstat (limited to 'src/mem/Bus.py')
| -rw-r--r-- | src/mem/Bus.py | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py index 447fc723e..45b1f1b0a 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -47,8 +47,6 @@ class BaseBus(MemObject): abstract = True slave = VectorSlavePort("vector port for connecting masters") master = VectorMasterPort("vector port for connecting slaves") - # Override the default clock - clock = '1GHz' header_cycles = Param.Cycles(1, "cycles of overhead per transaction") width = Param.Unsigned(8, "bus width (bytes)") block_size = Param.Unsigned(64, "The default block size if not set by " \ |