summaryrefslogtreecommitdiff
path: root/src/mem/Bus.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/Bus.py')
-rw-r--r--src/mem/Bus.py8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py
index e8e03ccb4..34d9ae664 100644
--- a/src/mem/Bus.py
+++ b/src/mem/Bus.py
@@ -43,6 +43,7 @@ from MemObject import MemObject
from System import System
from m5.params import *
from m5.proxy import *
+from m5.SimObject import SimObject
class BaseBus(MemObject):
type = 'BaseBus'
@@ -74,3 +75,10 @@ class CoherentBus(BaseBus):
cxx_header = "mem/coherent_bus.hh"
system = Param.System(Parent.any, "System that the bus belongs to.")
+
+class SnoopFilter(SimObject):
+ type = 'SnoopFilter'
+ cxx_header = "mem/snoop_filter.hh"
+ lookup_latency = Param.Cycles(3, "lookup latency (cycles)")
+
+ system = Param.System(Parent.any, "System that the bus belongs to.")