diff options
Diffstat (limited to 'src/mem/Bus.py')
| -rw-r--r-- | src/mem/Bus.py | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py index ca0f40e1e..e8e03ccb4 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -52,8 +52,6 @@ class BaseBus(MemObject): master = VectorMasterPort("vector port for connecting slaves") header_cycles = Param.Cycles(1, "cycles of overhead per transaction") width = Param.Unsigned(8, "bus width (bytes)") - block_size = Param.Unsigned(64, "The default block size if not set by " \ - "any connected module") # The default port can be left unconnected, or be used to connect # a default slave port |