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Diffstat (limited to 'src/mem/Bus.py')
| -rw-r--r-- | src/mem/Bus.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py index d24cefa62..447fc723e 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -50,9 +50,9 @@ class BaseBus(MemObject): # Override the default clock clock = '1GHz' header_cycles = Param.Cycles(1, "cycles of overhead per transaction") - width = Param.Int(8, "bus width (bytes)") - block_size = Param.Int(64, "The default block size if not set by " \ - "any connected module") + width = Param.Unsigned(8, "bus width (bytes)") + block_size = Param.Unsigned(64, "The default block size if not set by " \ + "any connected module") # The default port can be left unconnected, or be used to connect # a default slave port |