diff options
Diffstat (limited to 'src/mem/Bus.py')
| -rw-r--r-- | src/mem/Bus.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py index b398af959..d24cefa62 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -49,7 +49,7 @@ class BaseBus(MemObject): master = VectorMasterPort("vector port for connecting slaves") # Override the default clock clock = '1GHz' - header_cycles = Param.Int(1, "cycles of overhead per transaction") + header_cycles = Param.Cycles(1, "cycles of overhead per transaction") width = Param.Int(8, "bus width (bytes)") block_size = Param.Int(64, "The default block size if not set by " \ "any connected module") |