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-rw-r--r--src/mem/Bus.py4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py
index 4637b0ebc..ca0f40e1e 100644
--- a/src/mem/Bus.py
+++ b/src/mem/Bus.py
@@ -40,7 +40,9 @@
# Andreas Hansson
from MemObject import MemObject
+from System import System
from m5.params import *
+from m5.proxy import *
class BaseBus(MemObject):
type = 'BaseBus'
@@ -72,3 +74,5 @@ class NoncoherentBus(BaseBus):
class CoherentBus(BaseBus):
type = 'CoherentBus'
cxx_header = "mem/coherent_bus.hh"
+
+ system = Param.System(Parent.any, "System that the bus belongs to.")