diff options
Diffstat (limited to 'src/mem/DRAMCtrl.py')
| -rw-r--r-- | src/mem/DRAMCtrl.py | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py index 3145751cc..f78a7370d 100644 --- a/src/mem/DRAMCtrl.py +++ b/src/mem/DRAMCtrl.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2016 ARM Limited +# Copyright (c) 2012-2018 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -45,6 +45,7 @@ # Erfan Azarkhish from m5.params import * +from m5.proxy import * from AbstractMemory import * # Enum for memory scheduling algorithms, currently First-Come @@ -183,6 +184,13 @@ class DRAMCtrl(AbstractMemory): # for CAS-to-CAS delay for bursts to different bank groups tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") + # Write-to-Write delay for bursts to the same bank group + # only utilized with bank group architectures; set to 0 for default case + # This will be used to enable different same bank group delays + # for writes versus reads + tCCD_L_WR = Param.Latency(Self.tCCD_L, + "Same bank group Write to Write delay") + # time taken to complete one refresh cycle (N rows in all banks) tRFC = Param.Latency("Refresh cycle time") |