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Diffstat (limited to 'src/mem/PhysicalMemory.py')
| -rw-r--r-- | src/mem/PhysicalMemory.py | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/src/mem/PhysicalMemory.py b/src/mem/PhysicalMemory.py index c5f80b4c9..756117972 100644 --- a/src/mem/PhysicalMemory.py +++ b/src/mem/PhysicalMemory.py @@ -39,21 +39,3 @@ class PhysicalMemory(MemObject): latency_var = Param.Latency('0ns', "access variablity") zero = Param.Bool(False, "zero initialize memory") null = Param.Bool(False, "do not store data, always return zero") - -class DRAMMemory(PhysicalMemory): - type = 'DRAMMemory' - # Many of these should be observed from the configuration - cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed") - mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)") - mem_actpolicy = Param.String("open", "Open/Close policy") - memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct") - bus_width = Param.Int(16, "") - act_lat = Param.Latency("2ns", "RAS to CAS delay") - cas_lat = Param.Latency("1ns", "CAS delay") - war_lat = Param.Latency("2ns", "write after read delay") - pre_lat = Param.Latency("2ns", "precharge delay") - dpl_lat = Param.Latency("2ns", "data in to precharge delay") - trc_lat = Param.Latency("6ns", "row cycle delay") - num_banks = Param.Int(4, "Number of Banks") - num_cpus = Param.Int(4, "Number of CPUs connected to DRAM") - |