diff options
Diffstat (limited to 'src/mem/SConscript')
| -rw-r--r-- | src/mem/SConscript | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript index c351661b8..35f2e9ce4 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -39,28 +39,28 @@ if env['HAVE_PROTOBUF']: SimObject('AbstractMemory.py') SimObject('AddrMapper.py') SimObject('Bridge.py') -SimObject('Bus.py') SimObject('DRAMCtrl.py') SimObject('MemObject.py') SimObject('SimpleMemory.py') +SimObject('XBar.py') Source('abstract_mem.cc') Source('addr_mapper.cc') Source('bridge.cc') -Source('bus.cc') -Source('coherent_bus.cc') +Source('coherent_xbar.cc') Source('dram_ctrl.cc') Source('mem_object.cc') Source('mport.cc') -Source('noncoherent_bus.cc') +Source('noncoherent_xbar.cc') Source('packet.cc') Source('port.cc') Source('packet_queue.cc') -Source('tport.cc') Source('port_proxy.cc') -Source('simple_mem.cc') Source('physical.cc') +Source('simple_mem.cc') Source('snoop_filter.cc') +Source('tport.cc') +Source('xbar.cc') if env['TARGET_ISA'] != 'null': Source('fs_translating_port_proxy.cc') @@ -74,13 +74,13 @@ if env['HAVE_DRAMSIM']: Source('dramsim2_wrapper.cc') Source('dramsim2.cc') -DebugFlag('BaseBus') -DebugFlag('BusAddrRanges') -DebugFlag('CoherentBus') -DebugFlag('NoncoherentBus') +DebugFlag('AddrRanges') +DebugFlag('BaseXBar') +DebugFlag('CoherentXBar') +DebugFlag('NoncoherentXBar') DebugFlag('SnoopFilter') -CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus', - 'NoncoherentBus', 'SnoopFilter']) +CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar', + 'SnoopFilter']) DebugFlag('Bridge') DebugFlag('CommMonitor') |