summaryrefslogtreecommitdiff
path: root/src/mem/SConscript
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/SConscript')
-rw-r--r--src/mem/SConscript4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 0b0017f81..87498d21d 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -32,8 +32,9 @@ Import('*')
SimObject('Bridge.py')
SimObject('Bus.py')
-SimObject('PhysicalMemory.py')
SimObject('MemObject.py')
+SimObject('PhysicalMemory.py')
+SimObject('RubyMemory.py')
Source('bridge.cc')
Source('bus.cc')
@@ -44,6 +45,7 @@ Source('physical.cc')
Source('port.cc')
Source('tport.cc')
Source('mport.cc')
+Source('rubymem.cc')
if env['FULL_SYSTEM']:
Source('vport.cc')