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-rw-r--r--src/mem/SConscript4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript
index ddd57d11b..c513004d2 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -40,15 +40,16 @@ SimObject('AbstractMemory.py')
SimObject('AddrMapper.py')
SimObject('Bridge.py')
SimObject('Bus.py')
+SimObject('DRAMCtrl.py')
SimObject('MemObject.py')
SimObject('SimpleMemory.py')
-SimObject('SimpleDRAM.py')
Source('abstract_mem.cc')
Source('addr_mapper.cc')
Source('bridge.cc')
Source('bus.cc')
Source('coherent_bus.cc')
+Source('dram_ctrl.cc')
Source('mem_object.cc')
Source('mport.cc')
Source('noncoherent_bus.cc')
@@ -59,7 +60,6 @@ Source('tport.cc')
Source('port_proxy.cc')
Source('simple_mem.cc')
Source('physical.cc')
-Source('simple_dram.cc')
if env['TARGET_ISA'] != 'null':
Source('fs_translating_port_proxy.cc')