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-rw-r--r--src/mem/SConscript7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 90b49067e..9096fad5c 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -66,6 +66,11 @@ if env['TARGET_ISA'] != 'null':
Source('se_translating_port_proxy.cc')
Source('page_table.cc')
+ if env['HAVE_DRAMSIM']:
+ SimObject('DRAMSim2.py')
+ Source('dramsim2_wrapper.cc')
+ Source('dramsim2.cc')
+
DebugFlag('BaseBus')
DebugFlag('BusAddrRanges')
DebugFlag('CoherentBus')
@@ -81,6 +86,8 @@ DebugFlag('MMU')
DebugFlag('MemoryAccess')
DebugFlag('PacketQueue')
+DebugFlag("DRAMSim2")
+
DebugFlag('ProtocolTrace')
DebugFlag('RubyCache')
DebugFlag('RubyCacheTrace')