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-rw-r--r--src/mem/SConscript9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 3ffb3503a..1961204f7 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -37,9 +37,11 @@ SimObject('MemObject.py')
Source('bridge.cc')
Source('bus.cc')
+Source('coherent_bus.cc')
Source('comm_monitor.cc')
Source('mem_object.cc')
Source('mport.cc')
+Source('noncoherent_bus.cc')
Source('packet.cc')
Source('port.cc')
Source('packet_queue.cc')
@@ -56,8 +58,13 @@ if env['TARGET_ISA'] != 'no':
Source('page_table.cc')
Source('physical.cc')
-DebugFlag('Bus')
+DebugFlag('BaseBus')
DebugFlag('BusAddrRanges')
+DebugFlag('CoherentBus')
+DebugFlag('NoncoherentBus')
+CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
+ 'NoncoherentBus'])
+
DebugFlag('BusBridge')
DebugFlag('CommMonitor')
DebugFlag('LLSC')