diff options
Diffstat (limited to 'src/mem/SConscript')
| -rw-r--r-- | src/mem/SConscript | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mem/SConscript b/src/mem/SConscript index ca89418b5..02d0aee73 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -36,11 +36,15 @@ if env['HAVE_PROTOBUF']: SimObject('CommMonitor.py') Source('comm_monitor.cc') +SimObject('AbstractMemory.py') SimObject('AddrMapper.py') SimObject('Bridge.py') SimObject('Bus.py') SimObject('MemObject.py') +SimObject('SimpleMemory.py') +SimObject('SimpleDRAM.py') +Source('abstract_mem.cc') Source('addr_mapper.cc') Source('bridge.cc') Source('bus.cc') @@ -53,18 +57,14 @@ Source('port.cc') Source('packet_queue.cc') Source('tport.cc') Source('port_proxy.cc') -Source('fs_translating_port_proxy.cc') -Source('se_translating_port_proxy.cc') +Source('simple_mem.cc') +Source('physical.cc') +Source('simple_dram.cc') -if env['TARGET_ISA'] != 'no': - SimObject('AbstractMemory.py') - SimObject('SimpleMemory.py') - SimObject('SimpleDRAM.py') - Source('abstract_mem.cc') - Source('simple_mem.cc') +if env['TARGET_ISA'] != 'null': + Source('fs_translating_port_proxy.cc') + Source('se_translating_port_proxy.cc') Source('page_table.cc') - Source('physical.cc') - Source('simple_dram.cc') DebugFlag('BaseBus') DebugFlag('BusAddrRanges') |