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Diffstat (limited to 'src/mem/SimpleDRAM.py')
| -rw-r--r-- | src/mem/SimpleDRAM.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py index 41bad9356..0e43a6a39 100644 --- a/src/mem/SimpleDRAM.py +++ b/src/mem/SimpleDRAM.py @@ -80,6 +80,10 @@ class SimpleDRAM(AbstractMemory): lines_per_rowbuffer = Param.Unsigned("Row buffer size in cache lines") ranks_per_channel = Param.Unsigned("Number of ranks per channel") banks_per_rank = Param.Unsigned("Number of banks per rank") + # only used for the address mapping as the controller by + # construction is a single channel and multiple controllers have + # to be instantiated for a multi-channel configuration + channels = Param.Unsigned(1, "Number of channels") # timing behaviour and constraints - all in nanoseconds |