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Diffstat (limited to 'src/mem/SimpleDRAM.py')
| -rw-r--r-- | src/mem/SimpleDRAM.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py index 64e9f272b..ec76542d8 100644 --- a/src/mem/SimpleDRAM.py +++ b/src/mem/SimpleDRAM.py @@ -170,7 +170,7 @@ class SimpleDRAM(AbstractMemory): # tRC - assumed to be 4 * tRP - # burst length for an access derived from peerBlockSize + # burst length for an access derived from the cache line size # A single DDR3 x64 interface (one command and address bus), with # default timings based on DDR3-1600 4 Gbit parts in an 8x8 |