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-rw-r--r--src/mem/SimpleDRAM.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py
index c87425610..3211f576a 100644
--- a/src/mem/SimpleDRAM.py
+++ b/src/mem/SimpleDRAM.py
@@ -57,6 +57,7 @@ class PageManage(Enum): vals = ['open', 'close']
# itself.
class SimpleDRAM(AbstractMemory):
type = 'SimpleDRAM'
+ cxx_header = "mem/simple_dram.hh"
# single-ported on the system interface side, instantiate with a
# bus in front of the controller for multiple ports