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Diffstat (limited to 'src/mem/SimpleDRAM.py')
| -rw-r--r-- | src/mem/SimpleDRAM.py | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py index a72bd518c..514ff3664 100644 --- a/src/mem/SimpleDRAM.py +++ b/src/mem/SimpleDRAM.py @@ -54,8 +54,10 @@ class MemSched(Enum): vals = ['fcfs', 'frfcfs'] # maximises parallelism. class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] -# Enum for the page policy, either open, open_adaptive or close. -class PageManage(Enum): vals = ['open', 'open_adaptive', 'close'] +# Enum for the page policy, either open, open_adaptive, close, or +# close_adaptive. +class PageManage(Enum): vals = ['open', 'open_adaptive', 'close', + 'close_adaptive'] # SimpleDRAM is a single-channel single-ported DRAM controller model # that aims to model the most important system-level performance |