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Diffstat (limited to 'src/mem/SimpleDRAM.py')
| -rw-r--r-- | src/mem/SimpleDRAM.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py index 1f44888e7..a72bd518c 100644 --- a/src/mem/SimpleDRAM.py +++ b/src/mem/SimpleDRAM.py @@ -90,6 +90,10 @@ class SimpleDRAM(AbstractMemory): addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") page_policy = Param.PageManage('open', "Page closure management policy") + # enforce a limit on the number of accesses per row + max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " + "closing"); + # pipeline latency of the controller and PHY, split into a # frontend part and a backend part, with reads and writes serviced # by the queues only seeing the frontend contribution, and reads |