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Diffstat (limited to 'src/mem/SimpleMemory.py')
| -rw-r--r-- | src/mem/SimpleMemory.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py index c47d04222..9361b45d8 100644 --- a/src/mem/SimpleMemory.py +++ b/src/mem/SimpleMemory.py @@ -47,3 +47,7 @@ class SimpleMemory(AbstractMemory): port = SlavePort("Slave ports") latency = Param.Latency('30ns', "Request to response latency") latency_var = Param.Latency('0ns', "Request to response latency variance") + # The memory bandwidth limit default is set to 12.8GB/s which is + # representative of a x64 DDR3-1600 channel. + bandwidth = Param.MemoryBandwidth('12.8GB/s', + "Combined read and write bandwidth") |