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Diffstat (limited to 'src/mem/SimpleMemory.py')
| -rw-r--r-- | src/mem/SimpleMemory.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py index 51de3374d..c47d04222 100644 --- a/src/mem/SimpleMemory.py +++ b/src/mem/SimpleMemory.py @@ -44,6 +44,6 @@ from AbstractMemory import * class SimpleMemory(AbstractMemory): type = 'SimpleMemory' - port = VectorSlavePort("Slave ports") + port = SlavePort("Slave ports") latency = Param.Latency('30ns', "Request to response latency") latency_var = Param.Latency('0ns', "Request to response latency variance") |