diff options
Diffstat (limited to 'src/mem/abstract_mem.cc')
| -rw-r--r-- | src/mem/abstract_mem.cc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc index dca0403fb..ec1be04e1 100644 --- a/src/mem/abstract_mem.cc +++ b/src/mem/abstract_mem.cc @@ -379,6 +379,13 @@ AbstractMemory::access(PacketPtr pkt) bytesRead[pkt->req->masterId()] += pkt->getSize(); if (pkt->req->isInstFetch()) bytesInstRead[pkt->req->masterId()] += pkt->getSize(); + } else if (pkt->isInvalidate()) { + // no need to do anything + // this clause is intentionally before the write clause: the only + // transaction that is both a write and an invalidate is + // WriteInvalidate, and for the sake of consistency, it does not + // write to memory. in a cacheless system, there are no WriteInv's + // because the Write -> WriteInvalidate rewrite happens in the cache. } else if (pkt->isWrite()) { if (writeOK(pkt)) { if (pmemAddr) { @@ -391,8 +398,6 @@ AbstractMemory::access(PacketPtr pkt) numWrites[pkt->req->masterId()]++; bytesWritten[pkt->req->masterId()] += pkt->getSize(); } - } else if (pkt->isInvalidate()) { - // no need to do anything } else { panic("unimplemented"); } |