summaryrefslogtreecommitdiff
path: root/src/mem/bridge.cc
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/bridge.cc')
-rw-r--r--src/mem/bridge.cc17
1 files changed, 13 insertions, 4 deletions
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 855f39de3..1f7d1d43a 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -136,10 +136,14 @@ Bridge::BridgeMasterPort::recvTimingResp(PacketPtr pkt)
DPRINTF(Bridge, "Request queue size: %d\n", transmitList.size());
- // @todo: We need to pay for this and not just zero it out
+ // technically the packet only reaches us after the header delay,
+ // and typically we also need to deserialise any payload (unless
+ // the two sides of the bridge are synchronous)
+ Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
pkt->headerDelay = pkt->payloadDelay = 0;
- slavePort.schedTimingResp(pkt, bridge.clockEdge(delay));
+ slavePort.schedTimingResp(pkt, bridge.clockEdge(delay) +
+ receive_delay);
return true;
}
@@ -191,10 +195,15 @@ Bridge::BridgeSlavePort::recvTimingReq(PacketPtr pkt)
}
if (!retryReq) {
- // @todo: We need to pay for this and not just zero it out
+ // technically the packet only reaches us after the header
+ // delay, and typically we also need to deserialise any
+ // payload (unless the two sides of the bridge are
+ // synchronous)
+ Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
pkt->headerDelay = pkt->payloadDelay = 0;
- masterPort.schedTimingReq(pkt, bridge.clockEdge(delay));
+ masterPort.schedTimingReq(pkt, bridge.clockEdge(delay) +
+ receive_delay);
}
}