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Diffstat (limited to 'src/mem/cache/BaseCache.py')
| -rw-r--r-- | src/mem/cache/BaseCache.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index df4602199..9ffe39981 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -69,4 +69,6 @@ class BaseCache(MemObject): mem_side = MasterPort("Port on side closer to MEM") addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port") system = Param.System(Parent.any, "System we belong to") + sequential_access = Param.Bool(False, + "Whether to access tags and data sequentially") tags = Param.BaseTags(LRU(), "Tag Store for LRU caches") |