diff options
Diffstat (limited to 'src/mem/cache/BaseCache.py')
| -rw-r--r-- | src/mem/cache/BaseCache.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 706a556ed..7f2c1cc6f 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012 ARM Limited +# Copyright (c) 2012-2013 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -42,7 +42,7 @@ from m5.params import * from m5.proxy import * from MemObject import MemObject from Prefetcher import BasePrefetcher - +from Tags import * class BaseCache(MemObject): type = 'BaseCache' @@ -70,3 +70,4 @@ class BaseCache(MemObject): mem_side = MasterPort("Port on side closer to MEM") addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port") system = Param.System(Parent.any, "System we belong to") + tags = Param.BaseTags(LRU(), "Tag Store for LRU caches") |