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Diffstat (limited to 'src/mem/cache/BaseCache.py')
| -rw-r--r-- | src/mem/cache/BaseCache.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index adc48a461..83b3c70c2 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -60,5 +60,5 @@ class BaseCache(MemObject): prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") cpu_side = SlavePort("Port on side closer to CPU") mem_side = MasterPort("Port on side closer to MEM") - addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port") + addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port") system = Param.System(Parent.any, "System we belong to") |