summaryrefslogtreecommitdiff
path: root/src/mem/cache/BaseCache.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/cache/BaseCache.py')
-rw-r--r--src/mem/cache/BaseCache.py17
1 files changed, 5 insertions, 12 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index f6d42b1ef..bef1b45d2 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -38,8 +38,6 @@ class BaseCache(MemObject):
block_size = Param.Int("block size in bytes")
latency = Param.Latency("Latency")
hash_delay = Param.Int(1, "time in cycles of hash access")
- lifo = Param.Bool(False,
- "whether this NIC partition should use LIFO repl. policy")
max_miss_count = Param.Counter(0,
"number of misses to handle before calling exit")
mshrs = Param.Int("number of MSHRs (max outstanding requests)")
@@ -47,9 +45,6 @@ class BaseCache(MemObject):
"always service demand misses first")
repl = Param.Repl(NULL, "replacement policy")
size = Param.MemorySize("capacity in bytes")
- split = Param.Bool(False, "whether or not this cache is split")
- split_size = Param.Int(0,
- "How many ways of the cache belong to CPU/LRU partition")
subblock_size = Param.Int(0,
"Size of subblock in IIC used for compression")
tgts_per_mshr = Param.Int("max number of accesses per MSHR")
@@ -57,12 +52,10 @@ class BaseCache(MemObject):
two_queue = Param.Bool(False,
"whether the lifo should have two queue replacement")
write_buffers = Param.Int(8, "number of write buffers")
- prefetch_miss = Param.Bool(False,
- "wheter you are using the hardware prefetcher from Miss stream")
- prefetch_access = Param.Bool(False,
- "wheter you are using the hardware prefetcher from Access stream")
+ prefetch_on_access = Param.Bool(False,
+ "notify the hardware prefetcher on every access (not just misses)")
prefetcher_size = Param.Int(100,
- "Number of entries in the harware prefetch queue")
+ "Number of entries in the hardware prefetch queue")
prefetch_past_page = Param.Bool(False,
"Allow prefetches to cross virtual page boundaries")
prefetch_serial_squash = Param.Bool(False,
@@ -74,9 +67,9 @@ class BaseCache(MemObject):
prefetch_policy = Param.Prefetch('none',
"Type of prefetcher to use")
prefetch_cache_check_push = Param.Bool(True,
- "Check if in cash on push or pop of prefetch queue")
+ "Check if in cache on push or pop of prefetch queue")
prefetch_use_cpu_id = Param.Bool(True,
- "Use the CPU ID to seperate calculations of prefetches")
+ "Use the CPU ID to separate calculations of prefetches")
prefetch_data_accesses_only = Param.Bool(False,
"Only prefetch on data not on instruction accesses")
cpu_side = Port("Port on side closer to CPU")