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Diffstat (limited to 'src/mem/cache/Cache.py')
| -rw-r--r-- | src/mem/cache/Cache.py | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py index a2fa4e90f..230131bdc 100644 --- a/src/mem/cache/Cache.py +++ b/src/mem/cache/Cache.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2013, 2015 ARM Limited +# Copyright (c) 2012-2013, 2015, 2018 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -120,3 +120,13 @@ class BaseCache(MemObject): class Cache(BaseCache): type = 'Cache' cxx_header = 'mem/cache/cache.hh' + + +class NoncoherentCache(BaseCache): + type = 'NoncoherentCache' + cxx_header = 'mem/cache/noncoherent_cache.hh' + + # This is typically a last level cache and any clean + # writebacks would be unnecessary traffic to the main memory. + writeback_clean = False + |