diff options
Diffstat (limited to 'src/mem/cache/Cache.py')
| -rw-r--r-- | src/mem/cache/Cache.py | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py index 230131bdc..8ffab911b 100644 --- a/src/mem/cache/Cache.py +++ b/src/mem/cache/Cache.py @@ -41,6 +41,7 @@ from m5.params import * from m5.proxy import * +from m5.SimObject import SimObject from MemObject import MemObject from Prefetcher import BasePrefetcher from ReplacementPolicies import * @@ -51,6 +52,24 @@ from Tags import * # exclusive. class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl'] +class WriteAllocator(SimObject): + type = 'WriteAllocator' + cxx_header = "mem/cache/cache.hh" + + # Control the limits for when the cache introduces extra delays to + # allow whole-line write coalescing, and eventually switches to a + # write-no-allocate policy. + coalesce_limit = Param.Unsigned(2, "Consecutive lines written before " + "delaying for coalescing") + no_allocate_limit = Param.Unsigned(12, "Consecutive lines written before" + " skipping allocation") + + delay_threshold = Param.Unsigned(8, "Number of delay quanta imposed on an " + "MSHR with write requests to allow for " + "write coalescing") + + block_size = Param.Int(Parent.cache_line_size, "block size in bytes") + class BaseCache(MemObject): type = 'BaseCache' @@ -116,6 +135,11 @@ class BaseCache(MemObject): clusivity = Param.Clusivity('mostly_incl', "Clusivity with upstream cache") + # The write allocator enables optimizations for streaming write + # accesses by first coalescing writes and then avoiding allocation + # in the current cache. Typically, this would be enabled in the + # data cache. + write_allocator = Param.WriteAllocator(NULL, "Write allocator") class Cache(BaseCache): type = 'Cache' |