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-rw-r--r--src/mem/cache/Cache.py4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index b2f478472..7a28136b5 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -44,11 +44,11 @@ from m5.proxy import *
from m5.SimObject import SimObject
from m5.objects.ClockedObject import ClockedObject
+from m5.objects.Compressors import BaseCacheCompressor
from m5.objects.Prefetcher import BasePrefetcher
from m5.objects.ReplacementPolicies import *
from m5.objects.Tags import *
-
# Enum for cache clusivity, currently mostly inclusive or mostly
# exclusive.
class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
@@ -105,6 +105,8 @@ class BaseCache(ClockedObject):
replacement_policy = Param.BaseReplacementPolicy(LRURP(),
"Replacement policy")
+ compressor = Param.BaseCacheCompressor(NULL, "Cache compressor.")
+
sequential_access = Param.Bool(False,
"Whether to access tags and data sequentially")