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-rw-r--r--src/mem/cache/Cache.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index 0a590c2ca..b2f478472 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -43,7 +43,7 @@ from m5.params import *
from m5.proxy import *
from m5.SimObject import SimObject
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
from m5.objects.Prefetcher import BasePrefetcher
from m5.objects.ReplacementPolicies import *
from m5.objects.Tags import *
@@ -72,7 +72,7 @@ class WriteAllocator(SimObject):
block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
-class BaseCache(MemObject):
+class BaseCache(ClockedObject):
type = 'BaseCache'
abstract = True
cxx_header = "mem/cache/base.hh"