diff options
Diffstat (limited to 'src/mem/cache/base.cc')
| -rw-r--r-- | src/mem/cache/base.cc | 218 |
1 files changed, 172 insertions, 46 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index b0fb3bc6c..27ff6961b 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -65,7 +65,7 @@ BaseCache::BaseCache(const Params *p) missCount(p->max_miss_count), drainEvent(NULL), addrRange(p->addr_range), - _numCpus(p->num_cpus) + system(p->system) { } @@ -143,11 +143,14 @@ BaseCache::regStats() const string &cstr = cmd.toString(); hits[access_idx] - .init(FullSystem ? (_numCpus + 1) : _numCpus) + .init(system->maxMasters()) .name(name() + "." + cstr + "_hits") .desc("number of " + cstr + " hits") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxMasters(); i++) { + hits[access_idx].subname(i, system->getMasterName(i)); + } } // These macros make it easier to sum the right subset of commands and @@ -163,16 +166,22 @@ BaseCache::regStats() demandHits .name(name() + ".demand_hits") .desc("number of demand (read+write) hits") - .flags(total) + .flags(total | nozero | nonan) ; demandHits = SUM_DEMAND(hits); + for (int i = 0; i < system->maxMasters(); i++) { + demandHits.subname(i, system->getMasterName(i)); + } overallHits .name(name() + ".overall_hits") .desc("number of overall hits") - .flags(total) + .flags(total | nozero | nonan) ; overallHits = demandHits + SUM_NON_DEMAND(hits); + for (int i = 0; i < system->maxMasters(); i++) { + overallHits.subname(i, system->getMasterName(i)); + } // Miss statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -180,26 +189,35 @@ BaseCache::regStats() const string &cstr = cmd.toString(); misses[access_idx] - .init(FullSystem ? (_numCpus + 1) : _numCpus) + .init(system->maxMasters()) .name(name() + "." + cstr + "_misses") .desc("number of " + cstr + " misses") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxMasters(); i++) { + misses[access_idx].subname(i, system->getMasterName(i)); + } } demandMisses .name(name() + ".demand_misses") .desc("number of demand (read+write) misses") - .flags(total) + .flags(total | nozero | nonan) ; demandMisses = SUM_DEMAND(misses); + for (int i = 0; i < system->maxMasters(); i++) { + demandMisses.subname(i, system->getMasterName(i)); + } overallMisses .name(name() + ".overall_misses") .desc("number of overall misses") - .flags(total) + .flags(total | nozero | nonan) ; overallMisses = demandMisses + SUM_NON_DEMAND(misses); + for (int i = 0; i < system->maxMasters(); i++) { + overallMisses.subname(i, system->getMasterName(i)); + } // Miss latency statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -207,26 +225,35 @@ BaseCache::regStats() const string &cstr = cmd.toString(); missLatency[access_idx] - .init(maxThreadsPerCPU) + .init(system->maxMasters()) .name(name() + "." + cstr + "_miss_latency") .desc("number of " + cstr + " miss cycles") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxMasters(); i++) { + missLatency[access_idx].subname(i, system->getMasterName(i)); + } } demandMissLatency .name(name() + ".demand_miss_latency") .desc("number of demand (read+write) miss cycles") - .flags(total) + .flags(total | nozero | nonan) ; demandMissLatency = SUM_DEMAND(missLatency); + for (int i = 0; i < system->maxMasters(); i++) { + demandMissLatency.subname(i, system->getMasterName(i)); + } overallMissLatency .name(name() + ".overall_miss_latency") .desc("number of overall miss cycles") - .flags(total) + .flags(total | nozero | nonan) ; overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); + for (int i = 0; i < system->maxMasters(); i++) { + overallMissLatency.subname(i, system->getMasterName(i)); + } // access formulas for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -238,23 +265,32 @@ BaseCache::regStats() .desc("number of " + cstr + " accesses(hits+misses)") .flags(total | nozero | nonan) ; - accesses[access_idx] = hits[access_idx] + misses[access_idx]; + + for (int i = 0; i < system->maxMasters(); i++) { + accesses[access_idx].subname(i, system->getMasterName(i)); + } } demandAccesses .name(name() + ".demand_accesses") .desc("number of demand (read+write) accesses") - .flags(total) + .flags(total | nozero | nonan) ; demandAccesses = demandHits + demandMisses; + for (int i = 0; i < system->maxMasters(); i++) { + demandAccesses.subname(i, system->getMasterName(i)); + } overallAccesses .name(name() + ".overall_accesses") .desc("number of overall (read+write) accesses") - .flags(total) + .flags(total | nozero | nonan) ; overallAccesses = overallHits + overallMisses; + for (int i = 0; i < system->maxMasters(); i++) { + overallAccesses.subname(i, system->getMasterName(i)); + } // miss rate formulas for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -266,23 +302,32 @@ BaseCache::regStats() .desc("miss rate for " + cstr + " accesses") .flags(total | nozero | nonan) ; - missRate[access_idx] = misses[access_idx] / accesses[access_idx]; + + for (int i = 0; i < system->maxMasters(); i++) { + missRate[access_idx].subname(i, system->getMasterName(i)); + } } demandMissRate .name(name() + ".demand_miss_rate") .desc("miss rate for demand accesses") - .flags(total) + .flags(total | nozero | nonan) ; demandMissRate = demandMisses / demandAccesses; + for (int i = 0; i < system->maxMasters(); i++) { + demandMissRate.subname(i, system->getMasterName(i)); + } overallMissRate .name(name() + ".overall_miss_rate") .desc("miss rate for overall accesses") - .flags(total) + .flags(total | nozero | nonan) ; overallMissRate = overallMisses / overallAccesses; + for (int i = 0; i < system->maxMasters(); i++) { + overallMissRate.subname(i, system->getMasterName(i)); + } // miss latency formulas for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -294,24 +339,33 @@ BaseCache::regStats() .desc("average " + cstr + " miss latency") .flags(total | nozero | nonan) ; - avgMissLatency[access_idx] = missLatency[access_idx] / misses[access_idx]; + + for (int i = 0; i < system->maxMasters(); i++) { + avgMissLatency[access_idx].subname(i, system->getMasterName(i)); + } } demandAvgMissLatency .name(name() + ".demand_avg_miss_latency") .desc("average overall miss latency") - .flags(total) + .flags(total | nozero | nonan) ; demandAvgMissLatency = demandMissLatency / demandMisses; + for (int i = 0; i < system->maxMasters(); i++) { + demandAvgMissLatency.subname(i, system->getMasterName(i)); + } overallAvgMissLatency .name(name() + ".overall_avg_miss_latency") .desc("average overall miss latency") - .flags(total) + .flags(total | nozero | nonan) ; overallAvgMissLatency = overallMissLatency / overallMisses; + for (int i = 0; i < system->maxMasters(); i++) { + overallAvgMissLatency.subname(i, system->getMasterName(i)); + } blocked_cycles.init(NUM_BLOCKED_CAUSES); blocked_cycles @@ -350,11 +404,14 @@ BaseCache::regStats() ; writebacks - .init(maxThreadsPerCPU) + .init(system->maxMasters()) .name(name() + ".writebacks") .desc("number of writebacks") - .flags(total) + .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxMasters(); i++) { + writebacks.subname(i, system->getMasterName(i)); + } // MSHR statistics // MSHR hit statistics @@ -363,26 +420,35 @@ BaseCache::regStats() const string &cstr = cmd.toString(); mshr_hits[access_idx] - .init(maxThreadsPerCPU) + .init(system->maxMasters()) .name(name() + "." + cstr + "_mshr_hits") .desc("number of " + cstr + " MSHR hits") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxMasters(); i++) { + mshr_hits[access_idx].subname(i, system->getMasterName(i)); + } } demandMshrHits .name(name() + ".demand_mshr_hits") .desc("number of demand (read+write) MSHR hits") - .flags(total) + .flags(total | nozero | nonan) ; demandMshrHits = SUM_DEMAND(mshr_hits); + for (int i = 0; i < system->maxMasters(); i++) { + demandMshrHits.subname(i, system->getMasterName(i)); + } overallMshrHits .name(name() + ".overall_mshr_hits") .desc("number of overall MSHR hits") - .flags(total) + .flags(total | nozero | nonan) ; overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); + for (int i = 0; i < system->maxMasters(); i++) { + overallMshrHits.subname(i, system->getMasterName(i)); + } // MSHR miss statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -390,26 +456,35 @@ BaseCache::regStats() const string &cstr = cmd.toString(); mshr_misses[access_idx] - .init(maxThreadsPerCPU) + .init(system->maxMasters()) .name(name() + "." + cstr + "_mshr_misses") .desc("number of " + cstr + " MSHR misses") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxMasters(); i++) { + mshr_misses[access_idx].subname(i, system->getMasterName(i)); + } } demandMshrMisses .name(name() + ".demand_mshr_misses") .desc("number of demand (read+write) MSHR misses") - .flags(total) + .flags(total | nozero | nonan) ; demandMshrMisses = SUM_DEMAND(mshr_misses); + for (int i = 0; i < system->maxMasters(); i++) { + demandMshrMisses.subname(i, system->getMasterName(i)); + } overallMshrMisses .name(name() + ".overall_mshr_misses") .desc("number of overall MSHR misses") - .flags(total) + .flags(total | nozero | nonan) ; overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); + for (int i = 0; i < system->maxMasters(); i++) { + overallMshrMisses.subname(i, system->getMasterName(i)); + } // MSHR miss latency statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -417,27 +492,36 @@ BaseCache::regStats() const string &cstr = cmd.toString(); mshr_miss_latency[access_idx] - .init(maxThreadsPerCPU) + .init(system->maxMasters()) .name(name() + "." + cstr + "_mshr_miss_latency") .desc("number of " + cstr + " MSHR miss cycles") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxMasters(); i++) { + mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); + } } demandMshrMissLatency .name(name() + ".demand_mshr_miss_latency") .desc("number of demand (read+write) MSHR miss cycles") - .flags(total) + .flags(total | nozero | nonan) ; demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); + for (int i = 0; i < system->maxMasters(); i++) { + demandMshrMissLatency.subname(i, system->getMasterName(i)); + } overallMshrMissLatency .name(name() + ".overall_mshr_miss_latency") .desc("number of overall MSHR miss cycles") - .flags(total) + .flags(total | nozero | nonan) ; overallMshrMissLatency = demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); + for (int i = 0; i < system->maxMasters(); i++) { + overallMshrMissLatency.subname(i, system->getMasterName(i)); + } // MSHR uncacheable statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -445,20 +529,26 @@ BaseCache::regStats() const string &cstr = cmd.toString(); mshr_uncacheable[access_idx] - .init(maxThreadsPerCPU) + .init(system->maxMasters()) .name(name() + "." + cstr + "_mshr_uncacheable") .desc("number of " + cstr + " MSHR uncacheable") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxMasters(); i++) { + mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); + } } overallMshrUncacheable .name(name() + ".overall_mshr_uncacheable_misses") .desc("number of overall MSHR uncacheable misses") - .flags(total) + .flags(total | nozero | nonan) ; overallMshrUncacheable = SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); + for (int i = 0; i < system->maxMasters(); i++) { + overallMshrUncacheable.subname(i, system->getMasterName(i)); + } // MSHR miss latency statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -466,21 +556,27 @@ BaseCache::regStats() const string &cstr = cmd.toString(); mshr_uncacheable_lat[access_idx] - .init(maxThreadsPerCPU) + .init(system->maxMasters()) .name(name() + "." + cstr + "_mshr_uncacheable_latency") .desc("number of " + cstr + " MSHR uncacheable cycles") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxMasters(); i++) { + mshr_uncacheable_lat[access_idx].subname(i, system->getMasterName(i)); + } } overallMshrUncacheableLatency .name(name() + ".overall_mshr_uncacheable_latency") .desc("number of overall MSHR uncacheable cycles") - .flags(total) + .flags(total | nozero | nonan) ; overallMshrUncacheableLatency = SUM_DEMAND(mshr_uncacheable_lat) + SUM_NON_DEMAND(mshr_uncacheable_lat); + for (int i = 0; i < system->maxMasters(); i++) { + overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); + } #if 0 // MSHR access formulas @@ -524,24 +620,33 @@ BaseCache::regStats() .desc("mshr miss rate for " + cstr + " accesses") .flags(total | nozero | nonan) ; - mshrMissRate[access_idx] = mshr_misses[access_idx] / accesses[access_idx]; + + for (int i = 0; i < system->maxMasters(); i++) { + mshrMissRate[access_idx].subname(i, system->getMasterName(i)); + } } demandMshrMissRate .name(name() + ".demand_mshr_miss_rate") .desc("mshr miss rate for demand accesses") - .flags(total) + .flags(total | nozero | nonan) ; demandMshrMissRate = demandMshrMisses / demandAccesses; + for (int i = 0; i < system->maxMasters(); i++) { + demandMshrMissRate.subname(i, system->getMasterName(i)); + } overallMshrMissRate .name(name() + ".overall_mshr_miss_rate") .desc("mshr miss rate for overall accesses") - .flags(total) + .flags(total | nozero | nonan) ; overallMshrMissRate = overallMshrMisses / overallAccesses; + for (int i = 0; i < system->maxMasters(); i++) { + overallMshrMissRate.subname(i, system->getMasterName(i)); + } // mshrMiss latency formulas for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -553,24 +658,33 @@ BaseCache::regStats() .desc("average " + cstr + " mshr miss latency") .flags(total | nozero | nonan) ; - avgMshrMissLatency[access_idx] = mshr_miss_latency[access_idx] / mshr_misses[access_idx]; + + for (int i = 0; i < system->maxMasters(); i++) { + avgMshrMissLatency[access_idx].subname(i, system->getMasterName(i)); + } } demandAvgMshrMissLatency .name(name() + ".demand_avg_mshr_miss_latency") .desc("average overall mshr miss latency") - .flags(total) + .flags(total | nozero | nonan) ; demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; + for (int i = 0; i < system->maxMasters(); i++) { + demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); + } overallAvgMshrMissLatency .name(name() + ".overall_avg_mshr_miss_latency") .desc("average overall mshr miss latency") - .flags(total) + .flags(total | nozero | nonan) ; overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; + for (int i = 0; i < system->maxMasters(); i++) { + overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); + } // mshrUncacheable latency formulas for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -582,32 +696,44 @@ BaseCache::regStats() .desc("average " + cstr + " mshr uncacheable latency") .flags(total | nozero | nonan) ; - avgMshrUncacheableLatency[access_idx] = mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; + + for (int i = 0; i < system->maxMasters(); i++) { + avgMshrUncacheableLatency[access_idx].subname(i, system->getMasterName(i)); + } } overallAvgMshrUncacheableLatency .name(name() + ".overall_avg_mshr_uncacheable_latency") .desc("average overall mshr uncacheable latency") - .flags(total) + .flags(total | nozero | nonan) ; overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; + for (int i = 0; i < system->maxMasters(); i++) { + overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); + } mshr_cap_events - .init(maxThreadsPerCPU) + .init(system->maxMasters()) .name(name() + ".mshr_cap_events") .desc("number of times MSHR cap was activated") - .flags(total) + .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxMasters(); i++) { + mshr_cap_events.subname(i, system->getMasterName(i)); + } //software prefetching stats soft_prefetch_mshr_full - .init(maxThreadsPerCPU) + .init(system->maxMasters()) .name(name() + ".soft_prefetch_mshr_full") .desc("number of mshr full events for SW prefetching instrutions") - .flags(total) + .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxMasters(); i++) { + soft_prefetch_mshr_full.subname(i, system->getMasterName(i)); + } mshr_no_allocate_misses .name(name() +".no_allocate_misses") |