diff options
Diffstat (limited to 'src/mem/cache/base.hh')
| -rw-r--r-- | src/mem/cache/base.hh | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index fded6fca6..3aaed4455 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -73,6 +73,7 @@ class BaseCache : public MemObject MSHRQueue_WriteBuffer }; + public: /** * Reasons for caches to be blocked. */ @@ -83,7 +84,6 @@ class BaseCache : public MemObject NUM_BLOCKED_CAUSES }; - public: /** * Reasons for cache to request a bus. */ @@ -94,7 +94,7 @@ class BaseCache : public MemObject NUM_REQUEST_CAUSES }; - private: + protected: class CachePort : public SimpleTimingPort { @@ -105,8 +105,6 @@ class BaseCache : public MemObject CachePort(const std::string &_name, BaseCache *_cache, const std::string &_label); - virtual void recvRangeChange() const; - virtual unsigned deviceBlockSize() const; bool recvRetryCommon(); @@ -117,16 +115,12 @@ class BaseCache : public MemObject const std::string label; public: - void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; } - void setBlocked(); void clearBlocked(); bool checkFunctional(PacketPtr pkt); - CachePort *otherPort; - bool blocked; bool mustSendRetry; @@ -144,7 +138,6 @@ class BaseCache : public MemObject } }; - public: //Made public so coherence can get at it. CachePort *cpuSidePort; CachePort *memSidePort; |