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-rw-r--r--src/mem/cache/base.hh11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index c13d27d42..47cbaf7a0 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -118,7 +118,7 @@ class BaseCache : public MemObject
* and the sendDeferredPacket of the timing port is modified to
* consider both the transmit list and the requests from the MSHR.
*/
- class CacheMasterPort : public QueuedPort
+ class CacheMasterPort : public QueuedMasterPort
{
public:
@@ -149,7 +149,7 @@ class BaseCache : public MemObject
CacheMasterPort(const std::string &_name, BaseCache *_cache,
PacketQueue &_queue) :
- QueuedPort(_name, _cache, _queue)
+ QueuedMasterPort(_name, _cache, _queue)
{ }
/**
@@ -157,7 +157,7 @@ class BaseCache : public MemObject
*
* @return always true
*/
- virtual bool isSnooping() { return true; }
+ virtual bool isSnooping() const { return true; }
};
/**
@@ -168,7 +168,7 @@ class BaseCache : public MemObject
* incoming requests. If blocked, the port will issue a retry once
* unblocked.
*/
- class CacheSlavePort : public QueuedPort
+ class CacheSlavePort : public QueuedSlavePort
{
public:
@@ -444,6 +444,9 @@ class BaseCache : public MemObject
virtual void init();
+ virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
+ virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1);
+
/**
* Query block size of a cache.
* @return The block size