diff options
Diffstat (limited to 'src/mem/cache/base.hh')
| -rw-r--r-- | src/mem/cache/base.hh | 659 |
1 files changed, 630 insertions, 29 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 69c481825..aacf09afb 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013, 2015-2016 ARM Limited + * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -40,6 +40,8 @@ * Authors: Erik Hallnor * Steve Reinhardt * Ron Dreslinski + * Andreas Hansson + * Nikos Nikoleris */ /** @@ -50,29 +52,40 @@ #ifndef __MEM_CACHE_BASE_HH__ #define __MEM_CACHE_BASE_HH__ -#include <algorithm> -#include <list> +#include <cassert> +#include <cstdint> #include <string> -#include <vector> -#include "base/logging.hh" +#include "base/addr_range.hh" #include "base/statistics.hh" #include "base/trace.hh" #include "base/types.hh" #include "debug/Cache.hh" #include "debug/CachePort.hh" +#include "enums/Clusivity.hh" +#include "mem/cache/blk.hh" #include "mem/cache/mshr_queue.hh" +#include "mem/cache/tags/base.hh" #include "mem/cache/write_queue.hh" +#include "mem/cache/write_queue_entry.hh" #include "mem/mem_object.hh" #include "mem/packet.hh" +#include "mem/packet_queue.hh" #include "mem/qport.hh" #include "mem/request.hh" -#include "params/BaseCache.hh" #include "sim/eventq.hh" -#include "sim/full_system.hh" +#include "sim/serialize.hh" #include "sim/sim_exit.hh" #include "sim/system.hh" +class BaseMasterPort; +class BasePrefetcher; +class BaseSlavePort; +class MSHR; +class MasterPort; +class QueueEntry; +struct BaseCacheParams; + /** * A basic cache interface. Implements some common functions for speed. */ @@ -141,6 +154,87 @@ class BaseCache : public MemObject }; /** + * Override the default behaviour of sendDeferredPacket to enable + * the memory-side cache port to also send requests based on the + * current MSHR status. This queue has a pointer to our specific + * cache implementation and is used by the MemSidePort. + */ + class CacheReqPacketQueue : public ReqPacketQueue + { + + protected: + + BaseCache &cache; + SnoopRespPacketQueue &snoopRespQueue; + + public: + + CacheReqPacketQueue(BaseCache &cache, MasterPort &port, + SnoopRespPacketQueue &snoop_resp_queue, + const std::string &label) : + ReqPacketQueue(cache, port, label), cache(cache), + snoopRespQueue(snoop_resp_queue) { } + + /** + * Override the normal sendDeferredPacket and do not only + * consider the transmit list (used for responses), but also + * requests. + */ + virtual void sendDeferredPacket(); + + /** + * Check if there is a conflicting snoop response about to be + * send out, and if so simply stall any requests, and schedule + * a send event at the same time as the next snoop response is + * being sent out. + */ + bool checkConflictingSnoop(Addr addr) + { + if (snoopRespQueue.hasAddr(addr)) { + DPRINTF(CachePort, "Waiting for snoop response to be " + "sent\n"); + Tick when = snoopRespQueue.deferredPacketReadyTime(); + schedSendEvent(when); + return true; + } + return false; + } + }; + + + /** + * The memory-side port extends the base cache master port with + * access functions for functional, atomic and timing snoops. + */ + class MemSidePort : public CacheMasterPort + { + private: + + /** The cache-specific queue. */ + CacheReqPacketQueue _reqQueue; + + SnoopRespPacketQueue _snoopRespQueue; + + // a pointer to our specific cache implementation + BaseCache *cache; + + protected: + + virtual void recvTimingSnoopReq(PacketPtr pkt); + + virtual bool recvTimingResp(PacketPtr pkt); + + virtual Tick recvAtomicSnoop(PacketPtr pkt); + + virtual void recvFunctionalSnoop(PacketPtr pkt); + + public: + + MemSidePort(const std::string &_name, BaseCache *_cache, + const std::string &_label); + }; + + /** * A cache slave port is used for the CPU-side port of the cache, * and it is basically a simple timing port that uses a transmit * list for responses to the CPU (or connected master). In @@ -181,8 +275,39 @@ class BaseCache : public MemObject }; - CacheSlavePort *cpuSidePort; - CacheMasterPort *memSidePort; + /** + * The CPU-side port extends the base cache slave port with access + * functions for functional, atomic and timing requests. + */ + class CpuSidePort : public CacheSlavePort + { + private: + + // a pointer to our specific cache implementation + BaseCache *cache; + + protected: + virtual bool recvTimingSnoopResp(PacketPtr pkt) override; + + virtual bool tryTiming(PacketPtr pkt) override; + + virtual bool recvTimingReq(PacketPtr pkt) override; + + virtual Tick recvAtomic(PacketPtr pkt) override; + + virtual void recvFunctional(PacketPtr pkt) override; + + virtual AddrRangeList getAddrRanges() const override; + + public: + + CpuSidePort(const std::string &_name, BaseCache *_cache, + const std::string &_label); + + }; + + CpuSidePort cpuSidePort; + MemSidePort memSidePort; protected: @@ -192,6 +317,31 @@ class BaseCache : public MemObject /** Write/writeback buffer */ WriteQueue writeBuffer; + /** Tag and data Storage */ + BaseTags *tags; + + /** Prefetcher */ + BasePrefetcher *prefetcher; + + /** + * Notify the prefetcher on every access, not just misses. + */ + const bool prefetchOnAccess; + + /** + * Temporary cache block for occasional transitory use. We use + * the tempBlock to fill when allocation fails (e.g., when there + * is an outstanding request that accesses the victim block) or + * when we want to avoid allocation (e.g., exclusive caches) + */ + CacheBlk *tempBlock; + + /** + * Upstream caches need this packet until true is returned, so + * hold it for deletion until a subsequent call + */ + std::unique_ptr<Packet> pendingDelete; + /** * Mark a request as in service (sent downstream in the memory * system), effectively making this MSHR the ordering point. @@ -217,18 +367,349 @@ class BaseCache : public MemObject } /** - * Determine if we should allocate on a fill or not. + * Determine whether we should allocate on a fill or not. If this + * cache is mostly inclusive with regards to the upstream cache(s) + * we always allocate (for any non-forwarded and cacheable + * requests). In the case of a mostly exclusive cache, we allocate + * on fill if the packet did not come from a cache, thus if we: + * are dealing with a whole-line write (the latter behaves much + * like a writeback), the original target packet came from a + * non-caching source, or if we are performing a prefetch or LLSC. + * + * @param cmd Command of the incoming requesting packet + * @return Whether we should allocate on the fill + */ + inline bool allocOnFill(MemCmd cmd) const + { + return clusivity == Enums::mostly_incl || + cmd == MemCmd::WriteLineReq || + cmd == MemCmd::ReadReq || + cmd == MemCmd::WriteReq || + cmd.isPrefetch() || + cmd.isLLSC(); + } + + /** + * Does all the processing necessary to perform the provided request. + * @param pkt The memory request to perform. + * @param blk The cache block to be updated. + * @param lat The latency of the access. + * @param writebacks List for any writebacks that need to be performed. + * @return Boolean indicating whether the request was satisfied. + */ + virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, + PacketList &writebacks); + + /* + * Handle a timing request that hit in the cache + * + * @param ptk The request packet + * @param blk The referenced block + * @param request_time The tick at which the block lookup is compete + */ + virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, + Tick request_time); + + /* + * Handle a timing request that missed in the cache + * + * Implementation specific handling for different cache + * implementations + * + * @param ptk The request packet + * @param blk The referenced block + * @param forward_time The tick at which we can process dependent requests + * @param request_time The tick at which the block lookup is compete + */ + virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, + Tick forward_time, + Tick request_time) = 0; + + /* + * Handle a timing request that missed in the cache + * + * Common functionality across different cache implementations + * + * @param ptk The request packet + * @param blk The referenced block + * @param mshr Any existing mshr for the referenced cache block + * @param forward_time The tick at which we can process dependent requests + * @param request_time The tick at which the block lookup is compete + */ + void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk, + Tick forward_time, Tick request_time); + + /** + * Performs the access specified by the request. + * @param pkt The request to perform. + */ + virtual void recvTimingReq(PacketPtr pkt); + + /** + * Handling the special case of uncacheable write responses to + * make recvTimingResp less cluttered. + */ + void handleUncacheableWriteResp(PacketPtr pkt); + + /** + * Service non-deferred MSHR targets using the received response + * + * Iterates through the list of targets that can be serviced with + * the current response. Any writebacks that need to performed + * must be appended to the writebacks parameter. + * + * @param mshr The MSHR that corresponds to the reponse + * @param pkt The response packet + * @param blk The reference block + * @param writebacks List of writebacks that need to be performed + */ + virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, + CacheBlk *blk, PacketList& writebacks) = 0; + + /** + * Handles a response (cache line fill/write ack) from the bus. + * @param pkt The response packet + */ + virtual void recvTimingResp(PacketPtr pkt); + + /** + * Snoops bus transactions to maintain coherence. + * @param pkt The current bus transaction. + */ + virtual void recvTimingSnoopReq(PacketPtr pkt) = 0; + + /** + * Handle a snoop response. + * @param pkt Snoop response packet + */ + virtual void recvTimingSnoopResp(PacketPtr pkt) = 0; + + /** + * Handle a request in atomic mode that missed in this cache + * + * Creates a downstream request, sends it to the memory below and + * handles the response. As we are in atomic mode all operations + * are performed immediately. + * + * @param pkt The packet with the requests + * @param blk The referenced block + * @param writebacks A list with packets for any performed writebacks + * @return Cycles for handling the request + */ + virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk, + PacketList &writebacks) = 0; + + /** + * Performs the access specified by the request. + * @param pkt The request to perform. + * @return The number of ticks required for the access. + */ + virtual Tick recvAtomic(PacketPtr pkt); + + /** + * Snoop for the provided request in the cache and return the estimated + * time taken. + * @param pkt The memory request to snoop + * @return The number of ticks required for the snoop. + */ + virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0; + + /** + * Performs the access specified by the request. + * + * @param pkt The request to perform. + * @param fromCpuSide from the CPU side port or the memory side port + */ + virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side); + + /** + * Handle doing the Compare and Swap function for SPARC. + */ + void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); + + /** + * Return the next queue entry to service, either a pending miss + * from the MSHR queue, a buffered write from the write buffer, or + * something from the prefetcher. This function is responsible + * for prioritizing among those sources on the fly. + */ + QueueEntry* getNextQueueEntry(); + + /** + * Insert writebacks into the write buffer + */ + virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0; + + /** + * Send writebacks down the memory hierarchy in atomic mode + */ + virtual void doWritebacksAtomic(PacketList& writebacks) = 0; + + /** + * Create an appropriate downstream bus request packet. + * + * Creates a new packet with the request to be send to the memory + * below, or nullptr if the current request in cpu_pkt should just + * be forwarded on. + * + * @param cpu_pkt The miss packet that needs to be satisfied. + * @param blk The referenced block, can be nullptr. + * @param needs_writable Indicates that the block must be writable + * even if the request in cpu_pkt doesn't indicate that. + * @return A packet send to the memory below + */ + virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, + bool needs_writable) const = 0; + + /** + * Determine if clean lines should be written back or not. In + * cases where a downstream cache is mostly inclusive we likely + * want it to act as a victim cache also for lines that have not + * been modified. Hence, we cannot simply drop the line (or send a + * clean evict), but rather need to send the actual data. + */ + const bool writebackClean; + + /** + * Writebacks from the tempBlock, resulting on the response path + * in atomic mode, must happen after the call to recvAtomic has + * finished (for the right ordering of the packets). We therefore + * need to hold on to the packets, and have a method and an event + * to send them. + */ + PacketPtr tempBlockWriteback; + + /** + * Send the outstanding tempBlock writeback. To be called after + * recvAtomic finishes in cases where the block we filled is in + * fact the tempBlock, and now needs to be written back. + */ + void writebackTempBlockAtomic() { + assert(tempBlockWriteback != nullptr); + PacketList writebacks{tempBlockWriteback}; + doWritebacksAtomic(writebacks); + tempBlockWriteback = nullptr; + } + + /** + * An event to writeback the tempBlock after recvAtomic + * finishes. To avoid other calls to recvAtomic getting in + * between, we create this event with a higher priority. + */ + EventFunctionWrapper writebackTempBlockAtomicEvent; + + /** + * Perform any necessary updates to the block and perform any data + * exchange between the packet and the block. The flags of the + * packet are also set accordingly. + * + * @param pkt Request packet from upstream that hit a block + * @param blk Cache block that the packet hit + * @param deferred_response Whether this request originally missed + * @param pending_downgrade Whether the writable flag is to be removed + */ + virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk, + bool deferred_response = false, + bool pending_downgrade = false); + + /** + * Maintain the clusivity of this cache by potentially + * invalidating a block. This method works in conjunction with + * satisfyRequest, but is separate to allow us to handle all MSHR + * targets before potentially dropping a block. + * + * @param from_cache Whether we have dealt with a packet from a cache + * @param blk The block that should potentially be dropped + */ + void maintainClusivity(bool from_cache, CacheBlk *blk); + + /** + * Handle a fill operation caused by a received packet. + * + * Populates a cache block and handles all outstanding requests for the + * satisfied fill request. This version takes two memory requests. One + * contains the fill data, the other is an optional target to satisfy. + * Note that the reason we return a list of writebacks rather than + * inserting them directly in the write buffer is that this function + * is called by both atomic and timing-mode accesses, and in atomic + * mode we don't mess with the write buffer (we just perform the + * writebacks atomically once the original request is complete). + * + * @param pkt The memory request with the fill data. + * @param blk The cache block if it already exists. + * @param writebacks List for any writebacks that need to be performed. + * @param allocate Whether to allocate a block or use the temp block + * @return Pointer to the new cache block. + */ + CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, + PacketList &writebacks, bool allocate); + + /** + * Allocate a new block and perform any necessary writebacks + * + * Find a victim block and if necessary prepare writebacks for any + * existing data. May return nullptr if there are no replaceable + * blocks. + * + * @param addr Physical address of the new block + * @param is_secure Set if the block should be secure + * @param writebacks A list of writeback packets for the evicted blocks + * @return the allocated block + */ + CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); + /** + * Evict a cache block. + * + * Performs a writeback if necesssary and invalidates the block + * + * @param blk Block to invalidate + * @return A packet with the writeback, can be nullptr + */ + M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0; + + /** + * Evict a cache block. + * + * Performs a writeback if necesssary and invalidates the block + * + * @param blk Block to invalidate + * @param writebacks Return a list of packets with writebacks + */ + virtual void evictBlock(CacheBlk *blk, PacketList &writebacks) = 0; + + /** + * Invalidate a cache block. + * + * @param blk Block to invalidate + */ + void invalidateBlock(CacheBlk *blk); + + /** + * Create a writeback request for the given block. + * + * @param blk The block to writeback. + * @return The writeback request for the block. + */ + PacketPtr writebackBlk(CacheBlk *blk); + + /** + * Create a writeclean request for the given block. * - * @param cmd Packet command being added as an MSHR target + * Creates a request that writes the block to the cache below + * without evicting the block from the current cache. * - * @return Whether we should allocate on a fill or not + * @param blk The block to write clean. + * @param dest The destination of the write clean operation. + * @param id Use the given packet id for the write clean operation. + * @return The generated write clean packet. */ - virtual bool allocOnFill(MemCmd cmd) const = 0; + PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id); /** * Write back dirty blocks in the cache using functional accesses. */ - virtual void memWriteback() override = 0; + virtual void memWriteback() override; + /** * Invalidates all blocks in the cache. * @@ -236,13 +717,14 @@ class BaseCache : public MemObject * memory. Make sure to call functionalWriteback() first if you * want the to write them to memory. */ - virtual void memInvalidate() override = 0; + virtual void memInvalidate() override; + /** * Determine if there are any dirty blocks in the cache. * - * \return true if at least one block is dirty, false otherwise. + * @return true if at least one block is dirty, false otherwise. */ - virtual bool isDirty() const = 0; + bool isDirty() const; /** * Determine if an address is in the ranges covered by this @@ -254,6 +736,11 @@ class BaseCache : public MemObject */ bool inRange(Addr addr) const; + /** + * Find next request ready time from among possible sources. + */ + Tick nextQueueReadyTime() const; + /** Block size of this cache */ const unsigned blkSize; @@ -293,6 +780,13 @@ class BaseCache : public MemObject bool forwardSnoops; /** + * Clusivity with respect to the upstream cache, determining if we + * fill into both this cache and the cache above on a miss. Note + * that we currently do not support strict clusivity policies. + */ + const Enums::Clusivity clusivity; + + /** * Is this cache read only, for example the instruction cache, or * table-walker cache. A cache that is read only should never see * any writes, and should never get any dirty data (and hence @@ -463,18 +957,18 @@ class BaseCache : public MemObject /** * Register stats for this object. */ - virtual void regStats() override; + void regStats() override; public: BaseCache(const BaseCacheParams *p, unsigned blk_size); - ~BaseCache() {} + ~BaseCache(); - virtual void init() override; + void init() override; - virtual BaseMasterPort &getMasterPort(const std::string &if_name, - PortID idx = InvalidPortID) override; - virtual BaseSlavePort &getSlavePort(const std::string &if_name, - PortID idx = InvalidPortID) override; + BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID) override; + BaseSlavePort &getSlavePort(const std::string &if_name, + PortID idx = InvalidPortID) override; /** * Query block size of a cache. @@ -548,7 +1042,7 @@ class BaseCache : public MemObject if (blocked == 0) { blocked_causes[cause]++; blockedCycle = curCycle(); - cpuSidePort->setBlocked(); + cpuSidePort.setBlocked(); } blocked |= flag; DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); @@ -568,7 +1062,7 @@ class BaseCache : public MemObject DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); if (blocked == 0) { blocked_cycles[cause] += curCycle() - blockedCycle; - cpuSidePort->clearBlocked(); + cpuSidePort.clearBlocked(); } } @@ -582,12 +1076,16 @@ class BaseCache : public MemObject */ void schedMemSideSendEvent(Tick time) { - memSidePort->schedSendEvent(time); + memSidePort.schedSendEvent(time); } - virtual bool inCache(Addr addr, bool is_secure) const = 0; + bool inCache(Addr addr, bool is_secure) const { + return tags->findBlock(addr, is_secure); + } - virtual bool inMissQueue(Addr addr, bool is_secure) const = 0; + bool inMissQueue(Addr addr, bool is_secure) const { + return mshrQueue.findMatch(addr, is_secure); + } void incMissCount(PacketPtr pkt) { @@ -607,6 +1105,109 @@ class BaseCache : public MemObject } + /** + * Cache block visitor that writes back dirty cache blocks using + * functional writes. + * + * @return Always returns true. + */ + bool writebackVisitor(CacheBlk &blk); + + /** + * Cache block visitor that invalidates all blocks in the cache. + * + * @warn Dirty cache lines will not be written back to memory. + * + * @return Always returns true. + */ + bool invalidateVisitor(CacheBlk &blk); + + /** + * Take an MSHR, turn it into a suitable downstream packet, and + * send it out. This construct allows a queue entry to choose a suitable + * approach based on its type. + * + * @param mshr The MSHR to turn into a packet and send + * @return True if the port is waiting for a retry + */ + virtual bool sendMSHRQueuePacket(MSHR* mshr); + + /** + * Similar to sendMSHR, but for a write-queue entry + * instead. Create the packet, and send it, and if successful also + * mark the entry in service. + * + * @param wq_entry The write-queue entry to turn into a packet and send + * @return True if the port is waiting for a retry + */ + bool sendWriteQueuePacket(WriteQueueEntry* wq_entry); + + /** + * Serialize the state of the caches + * + * We currently don't support checkpointing cache state, so this panics. + */ + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; + +}; + +/** + * Wrap a method and present it as a cache block visitor. + * + * For example the forEachBlk method in the tag arrays expects a + * callable object/function as their parameter. This class wraps a + * method in an object and presents callable object that adheres to + * the cache block visitor protocol. + */ +class CacheBlkVisitorWrapper : public CacheBlkVisitor +{ + public: + typedef bool (BaseCache::*VisitorPtr)(CacheBlk &blk); + + CacheBlkVisitorWrapper(BaseCache &_cache, VisitorPtr _visitor) + : cache(_cache), visitor(_visitor) {} + + bool operator()(CacheBlk &blk) override { + return (cache.*visitor)(blk); + } + + private: + BaseCache &cache; + VisitorPtr visitor; +}; + +/** + * Cache block visitor that determines if there are dirty blocks in a + * cache. + * + * Use with the forEachBlk method in the tag array to determine if the + * array contains dirty blocks. + */ +class CacheBlkIsDirtyVisitor : public CacheBlkVisitor +{ + public: + CacheBlkIsDirtyVisitor() + : _isDirty(false) {} + + bool operator()(CacheBlk &blk) override { + if (blk.isDirty()) { + _isDirty = true; + return false; + } else { + return true; + } + } + + /** + * Does the array contain a dirty line? + * + * @return true if yes, false otherwise. + */ + bool isDirty() const { return _isDirty; }; + + private: + bool _isDirty; }; #endif //__MEM_CACHE_BASE_HH__ |