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-rw-r--r--src/mem/cache/base.hh10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 795347a0d..da72667b3 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -229,7 +229,15 @@ class BaseCache : public MemObject
/**
* The latency of a hit in this device.
*/
- int hitLatency;
+ const Tick hitLatency;
+
+ /**
+ * The latency of sending reponse to its upper level cache/core on a
+ * linefill. In most contemporary processors, the return path on a cache
+ * miss is much quicker that the hit latency. The responseLatency parameter
+ * tries to capture this latency.
+ */
+ const Tick responseLatency;
/** The number of targets for each MSHR. */
const int numTarget;