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-rw-r--r--src/mem/cache/base.hh2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 62e8ae126..2f1088609 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -324,12 +324,14 @@ class BaseCache : public MemObject
/** Total cycle latency of overall MSHR misses. */
Stats::Formula overallMshrUncacheableLatency;
+#if 0
/** The total number of MSHR accesses per command and thread. */
Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
/** The total number of demand MSHR accesses. */
Stats::Formula demandMshrAccesses;
/** The total number of MSHR accesses. */
Stats::Formula overallMshrAccesses;
+#endif
/** The miss rate in the MSHRs pre command and thread. */
Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];