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-rw-r--r--src/mem/cache/base.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index e522bc0c9..2a79fb354 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -269,7 +269,7 @@ class BaseCache : public MemObject
/**
* The address range to which the cache responds on the CPU side.
* Normally this is all possible memory addresses. */
- Range<Addr> addrRange;
+ AddrRangeList addrRanges;
public:
/** System we are currently operating in. */
@@ -439,7 +439,7 @@ class BaseCache : public MemObject
Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
- const Range<Addr> &getAddrRange() const { return addrRange; }
+ const AddrRangeList &getAddrRanges() const { return addrRanges; }
MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
{